GitHub - MarkYu98/riscv-sim: RISC-V simulator

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
cache		cache
include		include
mytest		mytest
test		test
.gitignore		.gitignore
Makefile		Makefile
config.json		config.json
riscv-sim.cpp		riscv-sim.cpp
riscv_config.hpp		riscv_config.hpp
riscv_isa.hpp		riscv_isa.hpp
riscv_memlib.c		riscv_memlib.c
riscv_memlib.h		riscv_memlib.h
riscv_proc.cpp		riscv_proc.cpp
riscv_proc.hpp		riscv_proc.hpp
riscv_syscall.c		riscv_syscall.c
riscv_syscall.h		riscv_syscall.h