-
Notifications
You must be signed in to change notification settings - Fork 0
/
riscv_proc.cpp
1323 lines (1244 loc) · 44.6 KB
/
riscv_proc.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include <riscv_proc.hpp>
#include <riscv_config.hpp>
#include <iostream>
#include <iomanip>
#include <sstream>
#include <string>
#include <assert.h>
#define GET_CACHE_CFG(config, name) CacheConfig(config.cache.name.size, \
config.cache.name.associativity, \
config.cache.name.size / \
(config.cache.name.block_size * config.cache.name.associativity), \
config.cache.name.writeback)
#define GET_CACHE_LATENCY(config, name) StorageLatency(config.latency.name##_hit, config.latency.name##_bus)
using namespace std;
REG alu_calc(REG src1, REG src2, unsigned ALU_FUNC)
{
switch (ALU_FUNC) {
case ALU_ADD:
return (SREG)src1 + (SREG)src2;
case ALU_SUB:
return (SREG)src1 - (SREG)src2;
case ALU_SLL:
return src1 << (src2 & 0x3f);
case ALU_SLT:
return ((SREG)src1 < (SREG)src2) ? 1 : 0;
case ALU_SLTU:
return (src1 < src2) ? 1 : 0;
case ALU_XOR:
return src1 ^ src2;
case ALU_SRL:
return src1 >> (src2 & 0x3f);
case ALU_SRA:
return REG((SREG(src1)) >> (src2 & 0x3f));
case ALU_OR:
return src1 | src2;
case ALU_AND:
return src1 & src2;
case ALU_ADDW:
return REG(SREG(int(src1 + src2)));
case ALU_SUBW:
return REG(SREG(int(src1 - src2)));
case ALU_SLLW:
return REG(SREG(int(src1 << (src2 & 0x3f))));
case ALU_SRLW:
return REG(SREG(int(src1 >> (src2 & 0x3f))));
case ALU_SRAW:
return REG(SREG(int((SREG(src1)) >> (src2 & 0x3f))));
case ALU_MUL:
// return REG(__int128_t(src1 * src2) & (((__int128_t)1<<(sizeof(REG)*8))-1));
return REG(SREG(src1) * SREG(src2));
case ALU_MULH:
return REG((__int128_t(SREG(src1)) * __int128_t(SREG(src2))) >> (sizeof(REG)*8));
case ALU_MULHSU:
return REG((__int128_t(SREG(src1)) * __int128_t(src2)) >> (sizeof(REG)*8));
case ALU_MULHU:
return REG((__int128_t(src1) * __int128_t(src2)) >> (sizeof(REG)*8));
case ALU_MULW:
return REG(SREG(int(src1) * int(src2)));
case ALU_DIV:
if (src2 == 0) return REG(-1);
return (SREG)src1 / (SREG)src2;
case ALU_DIVU:
if (src2 == 0) return REG(-1);
return src1 / src2;
case ALU_DIVW:
if (src2 == 0) return REG(-1);
return REG(SREG(int(src1) / int(src2)));
case ALU_DIVUW:
if (src2 == 0) return REG(-1);
return REG(SREG(unsigned(src1) / unsigned(src2)));
case ALU_REM:
if (src2 == 0) return src1;
return (SREG)src1 % (SREG)src2;
case ALU_REMU:
if (src2 == 0) return src1;
return src1 % src2;
case ALU_REMW:
if (src2 == 0) return (int)src1;
return REG(SREG(int(src1) % int(src2)));
case ALU_REMUW:
if (src2 == 0) return (unsigned)src1;
return REG(SREG(unsigned(src1) % unsigned(src2)));
default:
return 0;
}
}
string dec2hex(size_t i)
{
return dec2hex(i, 0);
}
string dec2hex(size_t i, size_t bytes)
{
stringstream ioss;
string s_temp;
ioss << hex << i;
ioss >> s_temp;
if (bytes == 0) return s_temp;
string s(bytes * 2 - s_temp.size(), '0');
s += s_temp;
return s;
}
static string reg_format(REG num, size_t bytes)
{
string full = dec2hex(num, sizeof(REG));
string res = "";
if (bytes <= 4) {
res += full.substr(full.size() - bytes * 2, full.size()) + "\t";
if (bytes == 1)
res += to_string(int(char(num)));
else if (bytes == 2)
res += to_string(short(num));
else if (bytes == 4)
res += to_string(int(num));
return res;
}
for (int i = bytes / 4; i > 0; i --) {
size_t start = full.size() - i * 8;
res += full.substr(start, start+8) + ' ';
}
res += "\t" + to_string(SREG(num));
return res;
}
string& trim(string &s)
{
if (s.empty()) return s;
s.erase(0,s.find_first_not_of(" "));
s.erase(s.find_last_not_of(" ") + 1);
return s;
}
ostream & operator << (ostream &os, const RISCV_inst &inst)
{
os << dec << dec2hex(inst.raw_inst, sizeof(inst.raw_inst)) << "\t";
switch (inst.type) {
case IT_R:
os << R_INST_NAME[inst.subtype.type_r] << " " << R_NAMES[inst.inst.inst_r.rd]
<< "," << R_NAMES[inst.inst.inst_r.rs1] << "," << R_NAMES[inst.inst.inst_r.rs2];
break;
case IT_I:
os << I_INST_NAME[inst.subtype.type_i];
if (inst.inst.inst_i.opcode == 0x73)
break;
os << " " << R_NAMES[inst.inst.inst_i.rd] << ",";
if (inst.inst.inst_i.opcode == 0x03)
os << inst.inst.inst_i.imm << "(" << R_NAMES[inst.inst.inst_i.rs1] << ")";
else
os << R_NAMES[inst.inst.inst_i.rs1] << "," << inst.inst.inst_i.imm;
break;
case IT_S:
os << S_INST_NAME[inst.subtype.type_s] << " " << R_NAMES[inst.inst.inst_s.rs2]
<< "," << inst.inst.inst_s.imm << "(" << R_NAMES[inst.inst.inst_s.rs1] << ")";
break;
case IT_SB:
os << SB_INST_NAME[inst.subtype.type_sb] << " " << R_NAMES[inst.inst.inst_sb.rs1]
<< "," << R_NAMES[inst.inst.inst_sb.rs2] << ",";
if (inst.inst.inst_sb.imm < 0) os << "-0x" << hex << -inst.inst.inst_sb.imm;
else os << "0x" << hex << inst.inst.inst_sb.imm;
break;
case IT_U:
os << U_INST_NAME[inst.subtype.type_u] << " " << R_NAMES[inst.inst.inst_u.rd]
<< ",0x" << hex << (inst.inst.inst_u.imm >> 12);
break;
case IT_UJ:
os << UJ_INST_NAME[inst.subtype.type_uj] << " " << R_NAMES[inst.inst.inst_uj.rd]
<< ",";
if (inst.inst.inst_uj.imm < 0) os << "-0x" << hex << -inst.inst.inst_uj.imm;
else os << "0x" << hex << inst.inst.inst_uj.imm;
break;
default:
os << "unimp";
}
}
ELF_SYMBOL::ELF_SYMBOL(uint8_t bind, uint8_t type, uint8_t other,
unsigned idx, ELFIO::Elf64_Addr value, ELFIO::Elf_Xword size,
ELFIO::Elf_Half section_index, string name) :
bind(bind), type(type), other(other), idx(idx), value(value),
size(size), section_index(section_index), name(name) {}
void CachedStorage::ClearStats()
{
StorageStats stats;
stats.access_time = 0;
L1.SetStats(stats);
L2.SetStats(stats);
L3.SetStats(stats);
memory.SetStats(stats);
}
void CachedStorage::SetConfig(CacheConfig cc1, CacheConfig cc2, CacheConfig cc3)
{
L1.SetConfig(cc1); L2.SetConfig(cc2); L3.SetConfig(cc3);
}
void CachedStorage::SetLatency(StorageLatency ltc1, StorageLatency ltc2, StorageLatency ltc3, StorageLatency ltcm)
{
L1.SetLatency(ltc1); L2.SetLatency(ltc2); L3.SetLatency(ltc3); memory.SetLatency(ltcm);
}
void CachedStorage::HandleRequest(size_t addr, int bytes, int read, char *content, int &time)
{
CacheConfig cc;
L1.GetConfig(cc);
size_t block_size = cc.size / (cc.associativity * cc.set_num);
size_t start = addr, end = addr + bytes;
time = 0;
while (addr < end) {
size_t block_bytes = min(ROUND_DOWN(addr, block_size) + block_size - addr, end - addr);
int _hit, _time;
if (content)
L1.HandleRequest(addr, block_bytes, read, content + addr - start, _hit, _time);
else
L1.HandleRequest(addr, block_bytes, read, nullptr, _hit, _time);
time += _time;
addr += block_bytes;
}
}
void CachedStorage::flush()
{
L1.flush(); L2.flush(); L3.flush();
}
void CachedStorage::StatsInfo(const StorageStats &s, bool ismem=true)
{
cout << " Access time (CPU cycles): " << dec << s.access_time << endl;
// cout << "L1 Cache access time (Nanoseconds): " << fixed << setprecision(2)
// << (double)s.access_time / cpu_freq_GHz << endl;
cout << " Access count: " << s.access_counter << endl;
if (ismem) {
cout << " Miss count: " << s.miss_num << endl;
cout << " - Miss rate: " << fixed << setprecision(2)
<< 100 * (double)s.miss_num / s.access_counter << "%" << endl;
cout << " Replace count: " << s.replace_num << endl;
cout << " Fetch count: " << s.fetch_num << endl;
}
cout << endl;
}
void CachedStorage::PrintStats()
{
StorageStats stats;
L1.GetStats(stats);
cout << "L1 Cache:" << endl;
StatsInfo(stats);
L2.GetStats(stats);
cout << "L2 Cache:" << endl;
StatsInfo(stats);
L3.GetStats(stats);
cout << "L3 Cache:" << endl;
StatsInfo(stats);
memory.GetStats(stats);
cout << "memory:" << endl;
StatsInfo(stats, false);
}
bool RISCV_proc::get_symbol(const string &symbol, ELF_SYMBOL** psym)
{
for (auto &sym : symtab) {
if (sym.name.compare(symbol) == 0) {
*psym = &sym;
return true;
}
}
return false;
}
void RISCV_proc::load_prog()
{
cout << "Loading ELF program into RISC-V simulator memory..." << endl;
ELFIO::Elf_Half sec_num = elf_reader.sections.size();
ELFIO::section *psec;
cout << "Reading ELF sections : ";
for (int i = 0; i < sec_num; i++) {
psec = elf_reader.sections[i];
cout << " [" << i << "] " << psec->get_name() << "\tflags: " << psec->get_flags() << "\t";
cout << "Addr: " << hex << "0x" << psec->get_address() << "\tSize: " << dec << psec->get_size() << endl;
if (psec->get_name().compare(".text") == 0)
text_sec = psec;
if (psec->get_type() == SHT_SYMTAB)
symtab_sec = psec;
}
cout << "Loading .symtab ... ";
const ELFIO::symbol_section_accessor symbols(elf_reader, symtab_sec);
symtab.clear();
symtab.reserve(symbols.get_symbols_num());
for (unsigned int j = 0; j < symbols.get_symbols_num(); j++) {
string name;
ELFIO::Elf64_Addr value;
ELFIO::Elf_Xword size;
ELFIO::Elf_Half section_index;
uint8_t bind, type, other;
symbols.get_symbol(j, name, value, size, bind,
type, section_index, other);
symtab.push_back(ELF_SYMBOL(bind, type, other, j, value, size, section_index, name));
}
cout << "Loaded." << endl;
// load_memory();
bool entry_setted = false;
if (config.set_entry_symbol || config.set_entry_addr) {
if (config.set_entry_symbol) entry_setted = set_entry_symbol(config.entry_symbol);
else entry_setted = set_entry_addr(config.entry_addr);
if (!entry_setted) cout << "Entry point cannot be overwrite! Using default." << endl;
}
else {
entry_addr = elf_reader.get_entry();
entry_literal = "<";
for (auto &sym : symtab)
if (sym.type == STT_FUNC && sym.value == entry_addr) {
entry_literal += sym.name + ", ";
break;
}
entry_literal += "0x" + dec2hex(entry_addr) + ">";
}
cout << "Entry point setted at " << entry_literal << "." << endl;
}
void RISCV_proc::load_memory()
{
ELFIO::Elf_Half seg_num = elf_reader.segments.size();
ELFIO::segment *pseg;
cout << "Loading ELF segments into user memory space ...";
reset_cache();
for (int i = 0; i < seg_num; i++) {
pseg = elf_reader.segments[i];
if (pseg->get_type() == PT_LOAD) { // Alloc: memcpy
uint8_t flags = 0;
if (pseg->get_flags() & PF_X) flags |= PTE_X;
if (pseg->get_flags() & PF_W) flags |= PTE_W;
write_memory(const_cast<char *>(pseg->get_data()), pseg->get_virtual_address(),
pseg->get_file_size(), flags);
write_memory(NULL, pseg->get_virtual_address() + pseg->get_file_size(),
pseg->get_memory_size() - pseg->get_file_size(), flags);
if (pseg->get_virtual_address() + pseg->get_memory_size() >= heap)
heap = ROUND_UP(pseg->get_virtual_address() + pseg->get_memory_size(), PGSIZE);
}
}
storage.flush();
cout << "Loaded." << endl;
}
bool RISCV_proc::set_entry_symbol(const string &symbol)
{
bool setted = false;
ELF_SYMBOL* psym = NULL;
cout << "Finding " << symbol << " in .symtab : ";
if (get_symbol(symbol, &psym)) {
setted = true;
cout << "[" << psym->idx << "] " << psym->name << "\tAddr: 0x" << hex << psym->value;
entry_addr = psym->value;
entry_offset = psym->value - text_sec->get_address();
cout << "\tOffset: 0x" << entry_offset << endl;
entry_literal = symbol;
entry_literal += ", 0x" + dec2hex(entry_addr);
return true;
}
return false;
}
bool RISCV_proc::set_entry_addr(size_t addr)
{
if (addr >= config.max_memory_addr) return false;
if (!PG_ALLOC(pg_table[PAGE(addr)]) || !PG_EXEC(pg_table[PAGE(addr)])) return false;
entry_addr = addr;
entry_literal = "0x" + dec2hex(addr);
return true;
}
RISCV_proc::RISCV_proc(const ELFIO::elfio &reader, const Config &config)
: elf_reader(reader), config(config)
{
memset(reg_ulong, 32, sizeof(reg_ulong));
}
RISCV_proc::~RISCV_proc()
{
clear_pg_table();
}
void RISCV_proc::reset_cache()
{
CacheConfig cc1 = GET_CACHE_CFG(config, l1);
CacheConfig cc2 = GET_CACHE_CFG(config, l2);
CacheConfig cc3 = GET_CACHE_CFG(config, l3);
storage.SetConfig(cc1, cc2, cc3);
StorageLatency ltc1 = GET_CACHE_LATENCY(config, l1);
StorageLatency ltc2 = GET_CACHE_LATENCY(config, l2);
StorageLatency ltc3 = GET_CACHE_LATENCY(config, l3);
StorageLatency ltcm = GET_CACHE_LATENCY(config, memory);
storage.SetLatency(ltc1, ltc2, ltc3, ltcm);
storage.ClearStats();
}
void RISCV_proc::read_memory(char *buf, size_t vaddr, size_t len)
{
size_t curpg, start = vaddr, end = vaddr + len;
while (vaddr < end) {
curpg = PAGE(vaddr);
pte_t &pte = pg_table[curpg];
if (!PG_ALLOC(pte)) cout << dec2hex(vaddr) << endl;
assert(PG_ALLOC(pte));
size_t read_bytes = min(curpg + PGSIZE - vaddr, end - vaddr);
int time;
storage.HandleRequest(pte.paddr + (vaddr - curpg), read_bytes, 1,
buf + vaddr - start, time);
pipe_cycle_count += time;
vaddr += read_bytes;
}
}
void RISCV_proc::write_memory(char *buf, size_t vaddr, size_t len, uint8_t flags = 0)
{
size_t curpg, start = vaddr, end = vaddr + len;
while (vaddr < end) {
curpg = PAGE(vaddr);
pte_t &pte = pg_table[curpg];
if (flags) alloc_page(curpg, flags);
else assert(PG_ALLOC(pte) && PG_WRITE(pte));
size_t write_bytes = min(curpg + PGSIZE - vaddr, end - vaddr);
int time;
if (buf)
storage.HandleRequest(pte.paddr + (vaddr - curpg), write_bytes, 0, buf + vaddr - start, time);
else
storage.HandleRequest(pte.paddr + (vaddr - curpg), write_bytes, 0, nullptr, time);
pipe_cycle_count += time;
vaddr += write_bytes;
}
}
void RISCV_proc::alloc_page(size_t vaddr, uint8_t flags)
{
pte_t &pte = pg_table[PAGE(vaddr)];
if (PG_ALLOC(pte)) return;
pte.paddr = storage.alloc_page();
pte.flags = (flags | PTE_P);
}
template<typename T> T RISCV_proc::memread(size_t vaddr)
{
if (!vaddr) return 0;
T res;
read_memory((char *)&res, vaddr, sizeof(T));
return res;
}
template<typename T> void RISCV_proc::memwrite(size_t vaddr, T val)
{
write_memory((char *)&val, vaddr, sizeof(T));
}
string RISCV_proc::read_string(size_t addr)
{
string res("");
char ch;
while ((ch = memread<char>(addr)) != '\0') {
res += ch;
addr += sizeof(char);
}
return res;
}
void RISCV_proc::fetch()
{
#ifndef PIPE
reg_D = calc_reg_D();
#else
reg_f = calc_reg_D();
#endif
}
void RISCV_proc::decode()
{
#ifndef PIPE
reg_E = calc_reg_E();
#else
reg_d = calc_reg_E();
#endif
}
void RISCV_proc::exec()
{
#ifndef PIPE
reg_M = calc_reg_M();
#else
reg_e = calc_reg_M();
#endif
}
void RISCV_proc::mem()
{
#ifndef PIPE
reg_W = calc_reg_W();
#else
reg_m = calc_reg_W();
#endif
}
void RISCV_proc::writeback()
{
bool setPC = false;
uint8_t opcode = reg_W.opcode;
if (opcode == 0x33 || opcode == 0x03 || opcode == 0x13 || opcode == 0x3b ||
opcode == 0x17 || opcode == 0x37 || opcode == 0x1b) {
if (reg_W.rd != R_ZERO) reg_ulong[reg_W.rd] = reg_W.res;
if (reg_W.rd == R_SP) {
assert(reg_W.res >= config.heap_max); // stack overflow
alloc_page(reg_W.res, PTE_W);
}
}
else if (opcode == 0x67 || opcode == 0x6f) {
if (reg_W.rd != R_ZERO) reg_ulong[reg_W.rd] = reg_W.val;
if (reg_W.rd == R_SP) {
assert(reg_W.res >= config.heap_max); // stack overflow
alloc_page(reg_W.val, PTE_W);
}
setPC = true;
}
else if (opcode == 0x63 && reg_W.cond)
setPC = true;
else if (opcode == 0x73) { // SYSCALL
reg_ulong[reg_W.rd] = 0;
pipe_cycle_count += config.latency.ecall;
switch (reg_W.val) {
case SYS_PRINT_I:
cout << "<stdout> " << dec << (long long) reg_W.res << endl;
break;
case SYS_PRINT_C:
cout << "<stdout> " << (char) reg_W.res << endl;
break;
case SYS_PRINT_S: {
string s = read_string(reg_W.res);
cout << "<stdout> " << s << endl;
} break;
case SYS_READ_I: {
long long x;
if (inputstream.rdbuf()->in_avail() == 0) {
cout << "<stdin> Waiting input: " << endl;
inputstream.clear();
inputstream.str();
string s;
getline(cin, s);
inputstream << s;
}
inputstream >> x;
reg_ulong[reg_W.rd] = REG(x);
} break;
case SYS_READ_C: {
char c;
if (inputstream.rdbuf()->in_avail() == 0) {
cout << "<stdin> Waiting input: " << endl;
inputstream.clear();
inputstream.str();
string s;
getline(cin, s);
inputstream << s;
}
inputstream >> c;
reg_ulong[reg_W.rd] = REG(SREG(c));
} break;
case SYS_SBRK: {
size_t old_heap = heap;
while (heap + PGSIZE < old_heap + reg_W.res) {
heap += PGSIZE;
assert(heap < config.heap_max); // heap overflow
alloc_page(heap, PTE_W);
}
heap = old_heap + reg_W.res;
assert(heap < config.heap_max); // heap overflow
alloc_page(heap, PTE_W);
reg_ulong[reg_W.rd] = REG(old_heap);
} break;
case SYS_HEAP_LO:
reg_ulong[reg_W.rd] = config.heap_base;
break;
case SYS_HEAP_HI:
reg_ulong[reg_W.rd] = config.heap_max;
break;
case SYS_EXIT:
flag_finished = true;
reg_ulong[reg_W.rd] = reg_W.res;
break;
}
}
#ifndef PIPE
if (setPC)
reg_F.PC = reg_W.res;
#endif
}
#ifdef PIPE
REG RISCV_proc::predict_PC(REG thisPC, int imm)
{
if (!config.branch_prediction.compare("always")) {
return thisPC + imm;
}
else if (!config.branch_prediction.compare("ftbnt")) {
if (imm > 0) return thisPC + imm;
else return thisPC + sizeof(raw_inst_t);
}
else if (!config.branch_prediction.compare("btfnt")) {
if (imm < 0) return thisPC + imm;
else return thisPC + sizeof(raw_inst_t);
}
return thisPC + sizeof(raw_inst_t);
}
void RISCV_proc::clock_tick()
{
CLOCK_TICK(w, F);
CLOCK_TICK(f, D);
CLOCK_TICK(d, E);
CLOCK_TICK(e, M);
CLOCK_TICK(m, W);
pipe_cycle_count++;
}
void RISCV_proc::set_pipe_control()
{
ctrl_F = ctrl_D = ctrl_E = ctrl_M = ctrl_W = PCTRL_NORMAL;
mispred = 0;
if (reg_E.opcode == 0x73 || reg_M.opcode == 0x73 || reg_W.opcode == 0x73) { // ECALL
ctrl_E = PCTRL_BUBBLE;
ctrl_D = PCTRL_STALL;
ctrl_F = PCTRL_STALL;
}
if (reg_E.opcode == 0x03 && (RS1(reg_D.inst) == reg_E.rd || RS2(reg_D.inst) == reg_E.rd)) { // LXX
ctrl_E = PCTRL_BUBBLE;
ctrl_D = PCTRL_STALL;
ctrl_F = PCTRL_STALL;
}
else if (OPCODE(reg_D.inst) == 0x67) { // JALR
ctrl_F = PCTRL_NORMAL;
ctrl_D = PCTRL_BUBBLE;
}
if (reg_E.opcode == 0x63) { // BXX
if ((reg_E.cond && (predict_PC(reg_E.src1, reg_E.src2) != (SREG)reg_E.src1 + (SREG)reg_E.src2)) ||
(!reg_E.cond && (predict_PC(reg_E.src1, reg_E.src2) == (SREG)reg_E.src1 + (SREG)reg_E.src2))) {
ctrl_E = PCTRL_BUBBLE;
ctrl_D = PCTRL_BUBBLE;
ctrl_F = PCTRL_NORMAL;
if (reg_E.cond) mispred = 1;
else mispred = 2;
}
}
}
PIPE_REG_F RISCV_proc::select_PC()
{
PIPE_REG_F result;
if (mispred) {
if (mispred == 1) result.PC = (SREG)reg_E.src1 + (SREG)reg_E.src2;
else result.PC = reg_e.PC + sizeof(raw_inst_t);
return result;
}
if (reg_d.opcode == 0x67) { // JALR in D
result.PC = reg_d.src1 + reg_d.src2;
return result;
}
result.PC = reg_F.PC;
switch (OPCODE(reg_f.inst)) {
case 0x6f: // JAL
result.PC = reg_F.PC + UJ_IMM(reg_f.inst);
break;
case 0x63: // BXX
result.PC = predict_PC(reg_F.PC, SB_IMM(reg_f.inst));
break;
case 0x67: // JALR
default:
result.PC = reg_F.PC + sizeof(raw_inst_t);
break;
}
return result;
}
void RISCV_proc::execute(size_t steps)
{
size_t s = 0;
do {
s++;
for (auto &bp : breakpoints)
if (bp.addr == reg_W.PC && bp.activated) {
cout << "Breakpoint at " << bp.literal << endl;
curbp = &bp;
bp.disable();
return;
}
if (curbp != nullptr) {
curbp->enable();
curbp = nullptr;
}
// Should in fact happen in parallel
// backward for data-forwarding to work correctly
writeback();
mem();
exec();
decode();
fetch();
reg_w = select_PC();
// Update the PIPE regs
clock_tick();
if (!reg_W.PC) s--;
// Set PIPE controls
set_pipe_control();
if (s == steps) break;
} while (!flag_finished);
inst_count += s;
}
#else
void RISCV_proc::execute(size_t steps)
{
size_t s = 0;
do {
s++;
for (auto &bp : breakpoints)
if (bp.addr == reg_F.PC && bp.activated) {
cout << "Breakpoint at " << bp.literal << endl;
curbp = &bp;
bp.disable();
return;
}
if (curbp != nullptr) {
curbp->enable();
curbp = nullptr;
}
fetch();
decode();
exec();
mem();
writeback();
pipe_cycle_count += 5;
if (s == steps) break;
} while (!flag_finished);
inst_count += s;
}
#endif
void RISCV_proc::run_simulator()
{
string shell_prompt = "> ";
string cmd, tmp;
int steps;
clear_regs();
inputstream.str("");
inputstream.clear();
breakpoints.clear();
curbp = nullptr;
clear_pg_table();
reg_F.PC = entry_addr;
reg_ulong[R_SP] = config.max_memory_addr - 8; // stack
heap = config.heap_base; // heap
load_memory();
reset_cache();
heap_base = heap;
alloc_page(reg_ulong[R_SP], PTE_W);
alloc_page(heap, PTE_W);
pipe_cycle_count = 0;
inst_count = 0;
flag_finished = flag_break = false;
cout << "Started at " << entry_literal << ": ";
cout << RISCV_inst(memread<raw_inst_t>(reg_F.PC)) << endl;
#ifdef PIPE
// Warmup
set_pipe_control();
execute(1);
#endif
while (1) {
if (flag_finished) {
cout << "Program exited with code: " << reg_ulong[R_A5] << endl;
break;
}
#ifdef PIPE
REG pc = reg_W.PC;
if (!PG_EXEC(pg_table[PAGE(pc)])) {
cout << "Fatal: PC Encountered unexecutable memory address! Execution stopped." << endl;
cout << dec2hex(pc) << endl;
break;
}
cout << "next inst.: <0x" << dec2hex(pc) << ">\t" << RISCV_inst(memread<raw_inst_t>(pc)) << endl;
#else
if (!PG_EXEC(pg_table[PAGE(reg_F.PC)])) {
cout << "Fatal: PC Encountered unexecutable memory address! Execution stopped." << endl;
break;
}
cout << "next inst.: <0x" << dec2hex(reg_F.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_F.PC)) << endl;
#endif
cout << shell_prompt;
tmp = cmd;
getline(cin, cmd);
if (trim(cmd).empty()) {
cmd = tmp;
cout << "Repeating command: " << cmd << endl;
}
if (cmd[0] == 's') {
if (cmd[1] >= '0' && cmd[1] <= '9')
steps = stoi(cmd.substr(1, cmd.size()));
else steps = 1;
execute(steps);
}
#ifdef PIPE
else if (cmd[0] == 'p') {
cout << "Pipeline Status: " << endl;
cout << "Fetch: <0x" << dec2hex(reg_F.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_F.PC)) << endl;
cout << "Decode:<0x" << dec2hex(reg_D.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_D.PC)) << endl;
cout << "Exec: <0x" << dec2hex(reg_E.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_E.PC)) << endl;
cout << "Mem: <0x" << dec2hex(reg_M.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_M.PC)) << endl;
cout << "WB: <0x" << dec2hex(reg_W.PC) << ">\t" << RISCV_inst(memread<raw_inst_t>(reg_W.PC)) << endl;
}
#endif
else if (cmd[0] == 'c') execute(0);
else if (cmd[0] == 'k') {
cout << "Program killed!" << endl;
break;
}
else if (cmd[0] == 'b') set_breakpoint(cmd);
else if (cmd[0] == 'i') summary();
else if (cmd[0] == 'd' || cmd[0] == 'e') {
int bpid;
try {
bpid = stoi(cmd.substr(1, cmd.size()));
} catch (invalid_argument) {
cout << "Error: Unidentified breakpoint id." << endl;
return;
}
if (bpid <= 0 || bpid > breakpoints.size()) {
cout << dec << "No breakpoint with id: " << bpid << endl;
return;
}
if (cmd[0] == 'e') {
breakpoints[bpid-1].enable();
cout << "Breakpoint [" << bpid << "] at " << breakpoints[bpid-1].literal;
cout << " enabled." << endl;
}
else if (cmd[0] == 'd') {
breakpoints[bpid-1].disable();
if (curbp == &breakpoints[bpid-1]) curbp = nullptr;
cout << "Breakpoint [" << bpid << "] at " << breakpoints[bpid-1].literal;
cout << " disabled." << endl;
}
}
else status(cmd);
}
summary(true);
}
void RISCV_proc::clear_pg_table()
{
pgtb_t::iterator it;
for (it = pg_table.begin(); it != pg_table.end(); it++) {
if (it->second.flags & PTE_P)
storage.free_page(it->second.paddr);
}
pg_table.clear();
}
void RISCV_proc::clear_regs()
{
memset(reg_ulong, 0, sizeof(reg_ulong));
reg_F = PIPE_REG_F();
reg_D = PIPE_REG_D();
reg_E = PIPE_REG_E();
reg_M = PIPE_REG_M();
reg_W = PIPE_REG_W();
}
void RISCV_proc::start()
{
load_prog();
print_config();
cout << endl;
cout << "Welcome to MarkYu's RISC-V simulator!" << endl;
shell();
exit();
}
void RISCV_proc::print_config()
{
cout << "-----------Simulator configurations------------" << endl;
cout << "Memory Heap: \tbase=0x" << dec2hex(config.heap_base) << "\tmax=0x" << dec2hex(config.heap_max) << endl;
cout << "Latency Settings (CPU cycles): " << dec << endl;
cout << " Instructions: mul:" << config.latency.mul << "\tmulw:" << config.latency.mulw <<
"\tdiv:" << config.latency.div << "\tdivw:" << config.latency.divw <<
"\tecall:" << config.latency.ecall << endl;
cout << " L1 Cache: Bus:" << config.latency.l1_bus << "\tHit:" << config.latency.l1_bus << endl;
cout << " L2 Cache: Bus:" << config.latency.l2_bus << "\tHit:" << config.latency.l2_bus << endl;
cout << " L3 Cache: Bus:" << config.latency.l3_bus << "\tHit:" << config.latency.l3_bus << endl;
cout << " Memory: Bus:" << config.latency.memory_bus << "\tHit:" << config.latency.memory_bus << endl;
cout << "Cache Settings: " << endl;
cout << " L1 Cache: Size:" << config.cache.l1.size << "B\t\tAssoc:" << config.cache.l1.associativity << endl;
cout << " Block Size:" << config.cache.l1.block_size << "B\t\tWrite Policy:"
<< (config.cache.l1.writeback ? "Write Back/Write Alloc" : "Write Through / No Write Alloc") << endl;
cout << " L2 Cache: Size:" << config.cache.l2.size << "B\t\tAssoc:" << config.cache.l2.associativity << endl;
cout << " Block Size:" << config.cache.l2.block_size << "B\tWrite Policy:"
<< (config.cache.l2.writeback ? "Write Back/Write Alloc" : "Write Through / No Write Alloc") << endl;
cout << " L3 Cache: Size:" << config.cache.l3.size << "B\t\tAssoc:" << config.cache.l3.associativity << endl;
cout << " Block Size:" << config.cache.l3.block_size << "B\tWrite Policy:"
<< (config.cache.l3.writeback ? "Write Back/Write Alloc" : "Write Through / No Write Alloc") << endl;
cout << "-----------------------------------------------" << endl;
}
void RISCV_proc::shell()
{
string shell_prompt = "RISCV-sim > ";
string cmd;
cout << "Enter 'r' to run the loaded program, enter 'q' to quit" << endl;
while (1) {
cout << shell_prompt;
getline(cin, cmd);
if (cmd[0] == 'q') break;
else if (cmd[0] == 'r') run_simulator();
else status(cmd);
}
}
void RISCV_proc::set_breakpoint(const string& cmd)
{
if (cmd.size() <= 2) {
cout << "Set breakpoint: \"b [address]\" or \"b *[symbol]\"." << endl;
return;
}
size_t addr;
stringstream ss;
string addr_s;
if (cmd[2] == '*') {
ELF_SYMBOL* psym;
ss << cmd.substr(3, cmd.size());
ss >> addr_s;
if (get_symbol(addr_s, &psym)) {
if (psym->type != STT_FUNC) {
cout << "Error: symbol type not allowed: " << addr_s << endl;
return;
}
addr = psym->value;
}
else {
cout << "Error: symbol not found: " << addr_s << endl;
return;
}
Breakpoint bp = Breakpoint(addr, "<"+addr_s+", 0x"+ dec2hex(addr)+">");
breakpoints.push_back(bp);
cout << "Breakpoint [" << dec << breakpoints.size() << "] set at " << bp.literal << endl;
}
else {
ss << cmd.substr(2, cmd.size());
ss >> addr_s;
try {
addr = ROUND_UP(stol(addr_s, 0, 0), sizeof(raw_inst_t));
} catch (invalid_argument) {
cout << "Error: Unidentified breakpoint address." << endl;
return;
}
if (addr < 0 || addr >= config.max_memory_addr)
cout << "Breakpoint: address out of range." << endl;
else {
if (!PG_ALLOC(pg_table[PAGE(addr)]) || !PG_EXEC(pg_table[PAGE(addr)]))
cout << "Breakpoint: address not executable, cannot set there." << endl;
else {
Breakpoint bp = Breakpoint(addr, "<0x"+ dec2hex(addr)+">");
breakpoints.push_back(bp);
cout << "Breakpoint [" << dec << breakpoints.size() << "] set at " << bp.literal << endl;
}
}
}
}
void RISCV_proc::status(const string& cmd)
{
int bytes = sizeof(long long);
if (cmd.size() <= 3) {
cout << "Unrecognized command: " << cmd << endl;
return;
}