Roadmap

The nearest objectives are to create performance model of classical 5-stage MIPS CPU using most of the features described by Hennessy and Patterson:

• Instruction caches
• Data bypassing and non-unified pipelines
• Data caches

and system-level compatibility

• Interrupts
• MARS System calls
• Memory translation

Mid-term targets are integration to existing simulation environments

• Encapsulation of ISA and switch to multi-ISA simulation: MIPS, RISC-V, OpenRISC, and ARM.
• Visualization with EduMIPS
• Interactive simulation through GDB
• Intergration to CEN64 simulation

Then, possible main directions are:

• Forking project to create model of out-of-order superscalar MIPS, like R10000.
• Align model with MIPSfpga.
• Verilog model of 5-stage MIPS CPU aligned with performance model.
• Multicore/Multithread modeling support with cache coherence models.