v1

.vscode/settings.json

@@ -0,0 +1,5 @@
+{
+    "files.associations": {
+        "features.h": "c"
+    }
+}

core/cvxif_example/cvxif_example_coprocessor.sv

@@ -22,6 +22,98 @@ module cvxif_example_coprocessor
     input  scoreboard_entry_t   commit_sbe_i  // from scoreboard 
 );
 
+  localparam Nb_of_regs = 151 ;
+  // =================================
+  // hugo modif : REGISTERS INTERFACE
+  // =================================
+
+  logic [Nb_of_regs-1:0][8:0] inputs;
+  logic signed   [Nb_of_regs-1:0][8:0] weights;
+  // reg wb pointer tocheck loading finished ot not. by convention
+  // in software, weights are loaded after so we get it from here
+  logic [7:0] reg_wb_pointer; // todo : fix size of pointer to log
+  cvxif_registers #(
+    .Nb_of_regs(Nb_of_regs),
+    .signed_regs(1)
+  ) weights_registers (
+    .clk_i(clk_i),
+    .rst_ni(rst_ni),
+    // if we is 1 in result, it means we executed and have to dump regs
+    .dump_i(x_result_o.we),
+    .we_i(registers_ctrl.we && registers_ctrl.is_weight),
+    .wb_data_i({registers_ctrl.data[7] , registers_ctrl.data}),
+    .regs_q(weights),
+    .wb_pointer_q(reg_wb_pointer)
+  );
+
+  cvxif_registers #(
+    .Nb_of_regs(Nb_of_regs),
+    .signed_regs(0)
+  ) inputs_registers (
+    .clk_i(clk_i),
+    .rst_ni(rst_ni),
+    // if we is 1 in result, it means we executed and have to dump regs
+    .dump_i(x_result_o.we),
+    .we_i(registers_ctrl.we && ~registers_ctrl.is_weight),
+    // ALWAYS unsigned so we sign extend on the 9th bit with 0
+    .wb_data_i({1'b0,registers_ctrl.data}),
+    .regs_q(inputs)
+  );
+
+  // ============================================
+  // hugo modif : EXTRACT DATA FROM COMMIT INSTR.
+  // ============================================
+
+  // added a type, because why not ?
+  typedef struct packed{
+    logic       we;
+    logic       is_weight; //if =1 the store in weights register and if =0, then store in inputs regs (16 each)
+    logic [7:0] data;
+  } destination_register_t;
+
+  // this store the onfos needed to manage the register interface
+  destination_register_t registers_ctrl;
+
+  always_comb begin : cvxif_commit
+    registers_ctrl.we = 1'b0;
+    registers_ctrl.is_weight = 0;
+    registers_ctrl.data = 0;
+    // commit if commit stage says its OK
+    if (commit_ack_i) begin
+      if(commit_sbe_i.op == LBC || commit_sbe_i.op == LBCU) begin
+        registers_ctrl.we = 1'b1;
+        // observation : LBC is used for weigths & LBCU is used for inputs !
+        registers_ctrl.is_weight = (commit_sbe_i.op == LBC) ? 1 : 0 ;
+        registers_ctrl.data = commit_sbe_i.result[7:0];
+      end 
+    end
+  end
+
+  // ======================================
+  // hugo modif : COMPUTE RESULT IN PRRALEL
+  // ======================================
+
+  // note : pipeline result tp respect timings !
+  logic signed [Nb_of_regs-1:0][17:0] mult_results_n, mult_results_q; 
+  logic signed [31:0] end_result;
+
+  integer i;
+  always_comb begin : compute_result
+    for(i=0;i<Nb_of_regs;i++) begin
+      mult_results_n[i] = signed'(inputs[i]) * signed'(weights[i]);
+    end
+  end
+
+  // compute result as a sum
+  integer j;
+  always_comb begin
+  end_result = 0;
+    for (integer j = 0; j < Nb_of_regs; j++) begin
+        end_result = signed'(end_result) + signed'(mult_results_q[j]);
+    end
+  end
+
+
   //Compressed interface
   logic               x_compressed_valid_i;
   logic               x_compressed_ready_o;
@@ -94,20 +186,26 @@ module cvxif_example_coprocessor
   x_issue_t req_i;
   x_issue_t req_o;
 
-
-
   assign instr_push = x_issue_resp_o.accept ? 1 : 0;
   assign instr_pop = (x_commit_i.x_commit_kill && x_commit_valid_i) || x_result_valid_o;
   assign x_issue_ready_q = ~fifo_full; // if something is in the fifo, the instruction is being processed
                                        // so we can't receive anything else
   assign req_i.req = x_issue_req_i;
   assign req_i.resp = x_issue_resp_o;
 
+  // check wether load is over 
+  logic load_finish_n, load_finish_q;
+  assign load_finish_n = reg_wb_pointer == (req_o.req.rs[1]);
+
   always_ff @(posedge clk_i or negedge rst_ni) begin : regs
     if (!rst_ni) begin
       x_issue_ready_o <= 1;
+      mult_results_q <= 0;
+      load_finish_q <= 0;
     end else begin
       x_issue_ready_o <= x_issue_ready_q;
+      mult_results_q <= mult_results_n;
+      load_finish_q <= load_finish_n;
     end
   end
 
@@ -130,24 +228,11 @@ module cvxif_example_coprocessor
       .pop_i     (instr_pop)
   );
 
-  logic [3:0] c;
-  counter #(
-      .WIDTH(4)
-  ) counter_i (
-      .clk_i     (clk_i),
-      .rst_ni    (rst_ni),
-      .clear_i   (~x_commit_i.x_commit_kill && x_commit_valid_i),
-      .en_i      (1'b1),
-      .load_i    (),
-      .down_i    (),
-      .d_i       (),
-      .q_o       (c),
-      .overflow_o()
-  );
-
+  // Assemble result for response
   always_comb begin
-    x_result_o.data    = req_o.req.rs[0] + req_o.req.rs[1] + (X_NUM_RS == 3 ? req_o.req.rs[2] : 0);
-    x_result_valid_o   = (c == x_result_o.data[3:0]) && ~fifo_empty ? 1 : 0;
+    x_result_o.data    = signed'(end_result + req_o.req.rs[0]);
+    // note : use RS2 (nb of total iterations) to see if all hav been loaded correctly !
+    x_result_valid_o   = ~fifo_empty && (load_finish_q);
     x_result_o.id      = req_o.req.id;
     x_result_o.rd      = req_o.req.instr[11:7];
     x_result_o.we      = req_o.resp.writeback & x_result_valid_o;

core/cvxif_example/cvxif_registers.sv

@@ -2,7 +2,7 @@
 // Desc : cvxif non-addressed registers
 
 module cvxif_registers #(
-    parameter Nb_of_regs = 150,
+    parameter Nb_of_regs,
     parameter signed_regs = 0,
     parameter reg_width = 9
 ) (
@@ -16,7 +16,9 @@ module cvxif_registers #(
     // actual data to load
     input logic [reg_width-1:0] wb_data_i,
     // register memory
-    output logic [Nb_of_regs-1:0][reg_width-1:0] regs_q
+    output logic [Nb_of_regs-1:0][reg_width-1:0] regs_q,
+    // output pointer to check when loading is finished
+    output logic [reg_width-1:0] wb_pointer_q
 );
 
 logic [reg_width-1:0] wb_pointer_q; // todo : fix this, supposed to be log_2(150)

core/cvxif_example/include/cvxif_instr_pkg.sv

@@ -16,7 +16,7 @@ package cvxif_instr_pkg;
   } copro_issue_resp_t;
 
   // 2 Possible RISCV instructions for Coprocessor
-  parameter int unsigned NbInstr = 2;
+  parameter int unsigned NbInstr = 3;
   parameter copro_issue_resp_t CoproInstr[NbInstr] = '{
       '{
           instr: 32'b00000_00_00000_00000_0_00_00000_0101011,  // custom1 opcode
@@ -41,6 +41,18 @@ package cvxif_instr_pkg;
               loadstore : 1'b0,
               exc : 1'b0
           }
+      },
+      '{
+          instr: 32'b00000_00_00000_00000_0_00_00000_0001011,  // custom2 opcode
+          mask: 32'b00000_00_00000_00000_0_00_00000_1111111,
+          resp : '{
+              accept : 1'b1,
+              writeback : 1'b1,
+              dualwrite : 1'b0,
+              dualread : 1'b0,
+              loadstore : 1'b0,
+              exc : 1'b0
+          }
       }
   };
 

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -18,7 +18,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF8En = 0;
   localparam CVA6ConfigFVecEn = 0;
 
-  localparam CVA6ConfigCvxifEn = 0;
+  localparam CVA6ConfigCvxifEn = 1;
   localparam CVA6ConfigCExtEn = 0;
   localparam CVA6ConfigZcbExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;

sw/app/Makefile

@@ -54,7 +54,8 @@ bmarks = \
 	dhrystone \
 	spmv \
 	pmp \
-	mnist
+	mnist \
+	hugo_test
 
 #--------------------------------------------------------------------
 # Build rules

sw/app/hugo_test/main.c

@@ -5,25 +5,51 @@ int main(void)
 {
         char a = -10;
         char* a_addr = &a;
+        int result;
+        int* res_addr = &result;
+        int nb_of_iter = 150;
 
-        for(char i = 0; i < 150; i++){
-                asm volatile("lbc x0 0(%0)"
-                : 
-                : "r" (a_addr)
+        for(char i = 0; i < nb_of_iter; i++){
+                asm volatile("lbc x0, 0(%0)"
+                        : 
+                        : "r" (a_addr)
                 );
-                asm volatile("lbcu x0 0(%0)"
-                : 
-                : "r" (a_addr)
+                asm volatile("lbcu x0, 0(%0)"
+                        : 
+                        : "r" (a_addr)
                 );
-                asm volatile("lb x0 0(%0)"
-                : 
-                : "r" (a_addr)
+                asm volatile("lb x0, 0(%0)"
+                        : 
+                        : "r" (a_addr)
                 );
-                asm volatile("lbu x0 0(%0)"
-                : 
-                : "r" (a_addr)
+                asm volatile("lbu x0, 0(%0)"
+                        : 
+                        : "r" (a_addr)
                 );
         }
+        // compute result
+        asm volatile ("mac %0 ,%0, %1, x0"
+                : "+r" (result)
+                : "r" (nb_of_iter)
+        );
+
+        // load result to check in simulatoion
+        asm volatile("lbcu x0, 0(%0)"
+                        : 
+                        : "r" (res_addr)
+                );
+        asm volatile("lbcu x0, 1(%0)"
+                        : 
+                        : "r" (res_addr)
+                );
+        asm volatile("lbcu x0, 2(%0)"
+                        : 
+                        : "r" (res_addr)
+                );
+        asm volatile("lbcu x0, 3(%0)"
+                        : 
+                        : "r" (res_addr)
+                );
 
         uint8_t message[12] = "Hello World";
         UART_init(&g_uart_0,