added cvxif regs in sources

0BAB1 · Apr 25, 2024 · 8703cdb · 8703cdb
1 parent d7d5a25
commit 8703cdb
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/corev_apu/fpga/scripts/run_cva6_fpga.tcl b/corev_apu/fpga/scripts/run_cva6_fpga.tcl
@@ -11,8 +11,6 @@
 #
 # Author:         Sebastien Jacq - sjthales on github.com
 
-#
-# Additional contributions by:
 #
 #
 # script Name:    run_cva6_fpga
@@ -60,6 +58,7 @@ set_property include_dirs { \
 	"../register_interface/include" \
 } [current_fileset]
 
+read_verilog -sv {../../core/cvxif_example/cvxif_registers.sv}
 source scripts/add_sources.tcl
 
 set_property top cva6_zybo_z7_20 [current_fileset]