8340643: RISC-V: Small refactoring for sub/subw macro-assembler routines

zifeihan · Sep 23, 2024 · 4d62e96 · 4d62e96
1 parent ab06a87
commit 4d62e96
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -2089,8 +2089,8 @@ void MacroAssembler::sub(Register Rd, Register Rn, int64_t decrement, Register t
     addi(Rd, Rn, -decrement);
   } else {
     assert_different_registers(Rn, temp);
-    li(temp, decrement);
-    sub(Rd, Rn, temp);
+    li(temp, -decrement);
+    add(Rd, Rn, temp);
   }
 }
 
@@ -2099,8 +2099,8 @@ void MacroAssembler::subw(Register Rd, Register Rn, int32_t decrement, Register
     addiw(Rd, Rn, -decrement);
   } else {
     assert_different_registers(Rn, temp);
-    li(temp, decrement);
-    subw(Rd, Rn, temp);
+    li(temp, -decrement);
+    addw(Rd, Rn, temp);
   }
 }