Skip to content
View yasnakateb's full-sized avatar
🥳
Shinra Tensei!
🥳
Shinra Tensei!
44 followers · 42 following
  • Madrid, Spain

Achievements

Achievement: StarstruckAchievement: QuickdrawAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Achievements

Achievement: StarstruckAchievement: QuickdrawAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Highlights

  • Pro

Block or report yasnakateb

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
yasnakateb/README.md

Hello, everyone! 😄

Exploring the details of how computers work at the fundamental level is my thing. Whether it's diving into processor design or understanding computer hardware, I'm always up for the challenge.

🎄 Current focus

🌱 Exploring CGRAs to unlock new levels of performance and efficiency in computing.

🌱 Delving into the world of RISC-V to understand its potential.

🌱 Learning about Productivity Systems to optimize how I work to become more efficient.

🌱 Building my Second Brain to connect the dots.

Yasna's GitHub Stats

Pinned Loading

  1. CGRAs CGRAs Public

    Coarse Grained Reconfigurable Arrays with Chisel3

    Scala 12

  2. Chatroom Chatroom Public

    🗣 Chatroom in Rust

    Rust 15 2

  3. PipelinedARM PipelinedARM Public

    💎 A 32-bit ARM Processor Implementation in Verilog HDL

    Verilog 18 3

  4. MIPSProcessor MIPSProcessor Public

    🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

    Verilog 6

  5. NoCRouter NoCRouter Public

    👶🏻 My first baby steps into the world of NoC

    Verilog 10 2

  6. PipelinedMIPS PipelinedMIPS Public

    🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

    Verilog 6 1