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Basic test suite complete
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DerelictDrone committed Nov 15, 2023
1 parent 61c5fc2 commit 24e0f0a
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Showing 8 changed files with 448 additions and 2 deletions.
6 changes: 5 additions & 1 deletion lua/autorun/cpu_load.lua
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ AddCSLuaFile("wire/zvm/zvm_features.lua")
AddCSLuaFile("wire/zvm/zvm_opcodes.lua")
AddCSLuaFile("wire/zvm/zvm_data.lua")


AddCSLuaFile("wire/cpulib.lua")
include("wire/cpulib.lua")

Expand All @@ -30,4 +31,7 @@ AddCSLuaFile("wire/cpu_default_data_files.lua")

if CLIENT then
include("wire/client/hlzasm/hc_compiler.lua")
end
end

AddCSLuaFile("wire/zvm/zvm_tests.lua")
include("wire/zvm/zvm_tests.lua")
2 changes: 1 addition & 1 deletion lua/wire/cpulib.lua
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
local INVALID_BREAKPOINT_IP = 2e7

CPULib = CPULib or {}
if CLIENT then
if CLIENT or TESTING then
-- Sourcecode available as compiled binary
CPULib.Source = ""
-- Compiled binary
Expand Down
28 changes: 28 additions & 0 deletions lua/wire/zvm/tests/example.lua
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
CPUTest = {}

function CPUTest:RunTest(VM,TestSuite)
CPUTest.VM = VM
CPUTest.TestSuite = TestSuite
TestSuite.Compile("x: INC R0 JMP x",nil,CPUTest.RunCPU,CPUTest.CompileError)
end

function CPUTest.RunCPU()
CPUTest.TestSuite.FlashData(CPUTest.VM,CPUTest.TestSuite.GetCompileBuffer()) -- upload compiled to virtual cpu
CPUTest.VM.Clk = 1
for i=0,4096 do
CPUTest.VM:RunStep()
end
-- False = no error, True = error
if CPUTest.VM.R0 == 4096 then
CPUTest.TestSuite.FinishTest(false)
else
print("R0 is not 4096! R0 is "..tostring(CPUTest.VM.R0))
CPUTest.TestSuite.FinishTest(true)
end
end

function CPUTest.CompileError()
print('hit a compile time error')
CPUTest.TestSuite.FinishTest(true)
end

17 changes: 17 additions & 0 deletions lua/wire/zvm/tests/intentional_compile_error.lua
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
CPUTest = {}

function CPUTest:RunTest(VM,TestSuite)
CPUTest.VM = VM
CPUTest.TestSuite = TestSuite
TestSuite.Compile("MOV R0,",nil,CPUTest.RunCPU,CPUTest.CompileError)
end

function CPUTest.RunCPU()
print('Compiler did not error when it should have!')
CPUTest.TestSuite.FinishTest(true)
end

function CPUTest.CompileError()
CPUTest.TestSuite.FinishTest(false)
end

28 changes: 28 additions & 0 deletions lua/wire/zvm/tests/intentional_failed_test.lua
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
CPUTest = {}

function CPUTest:RunTest(VM,TestSuite)
CPUTest.VM = VM
CPUTest.TestSuite = TestSuite
TestSuite.Compile("x: INC R0 JMP x",nil,CPUTest.RunCPU,CPUTest.CompileError)
end

function CPUTest.RunCPU()
CPUTest.TestSuite.FlashData(CPUTest.VM,CPUTest.TestSuite.GetCompileBuffer()) -- upload compiled to virtual cpu
CPUTest.VM.Clk = 1
for i=0,4096 do
CPUTest.VM:RunStep()
end
-- False = no error, True = error
if CPUTest.VM.R0 == 4095 then
CPUTest.TestSuite.FinishTest(false)
else
print("R0 is not 4095! R0 is "..tostring(CPUTest.VM.R0))
CPUTest.TestSuite.FinishTest(true)
end
end

function CPUTest.CompileError()
print('hit a compile time error')
CPUTest.TestSuite.FinishTest(true)
end

41 changes: 41 additions & 0 deletions lua/wire/zvm/tests/virtualiobus.lua
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
CPUTest = {}

function CPUTest:RunTest(VM,TestSuite)
CPUTest.VM = VM
CPUTest.TestSuite = TestSuite
TestSuite.Compile("MOV PORT0,1 MOV R0,PORT0",nil,CPUTest.RunCPU,CPUTest.CompileError)
end

function CPUTest.RunCPU()
CPUTest.TestSuite.FlashData(CPUTest.VM,CPUTest.TestSuite.GetCompileBuffer()) -- upload compiled to virtual cpu
local IOBus = CPUTest.TestSuite.CreateVirtualIOBus(4) -- get external IO device of size 4
CPUTest.TestSuite.Initialize(CPUTest.VM,nil,IOBus) -- reinitialize the CPU with the IOBus
IOBus.InPorts[0] = 24
CPUTest.VM.Clk = 1
for i=0,16 do
CPUTest.VM:RunStep()
end

-- False = no error, True = error
if IOBus:ReadCell(0) == 24 then
if IOBus.OutPorts[0] == 1 then
if CPUTest.VM.R0 == 24 then
CPUTest.TestSuite.FinishTest(false)
else
print("CPU failed to read input port! R0 = "..CPUTest.VM.R0)
CPUTest.TestSuite.FinishTest(true)
end
else
print("CPU failed to write to output port! Port0 = "..IOBus.OutPorts[0])
end
else
print("CPU wrote to input ports! "..tostring(IOBus:ReadCell(0)))
CPUTest.TestSuite.FinishTest(true)
end
end

function CPUTest.CompileError()
print('hit a compile time error')
CPUTest.TestSuite.FinishTest(true)
end

36 changes: 36 additions & 0 deletions lua/wire/zvm/tests/virtualmembus.lua
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
CPUTest = {}

function CPUTest:RunTest(VM,TestSuite)
CPUTest.VM = VM
CPUTest.TestSuite = TestSuite
TestSuite.Compile("CPUGET R0,43 MOV [R0],1 MOV R1,[R0]",nil,CPUTest.RunCPU,CPUTest.CompileError)
end

function CPUTest.RunCPU()
CPUTest.TestSuite.FlashData(CPUTest.VM,CPUTest.TestSuite.GetCompileBuffer()) -- upload compiled to virtual cpu
local bus = CPUTest.TestSuite.CreateVirtualMemBus(4) -- get external ram device of size 4
CPUTest.TestSuite.Initialize(CPUTest.VM,bus,nil) -- reinitialize the CPU with the membus
CPUTest.VM.Clk = 1
for i=0,16 do
CPUTest.VM:RunStep()
end

-- False = no error, True = error
if bus:ReadCell(0) == 1 then
if CPUTest.VM.R1 == 1 then
CPUTest.TestSuite.FinishTest(false)
else
print('CPU failed to read the bus! R1 was '..tostring(CPUTest.VM.R1))
CPUTest.TestSuite.FinishTest(true)
end
else
print("CPU failed to write to bus! "..tostring(bus:ReadCell(0)))
CPUTest.TestSuite.FinishTest(true)
end
end

function CPUTest.CompileError()
print('hit a compile time error')
CPUTest.TestSuite.FinishTest(true)
end

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