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minor update
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tinebp committed Sep 18, 2024
1 parent 8e3bd56 commit f0bff2a
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Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion hw/rtl/core/VX_lsu_slice.sv
Original file line number Diff line number Diff line change
Expand Up @@ -341,7 +341,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
.core_req_tag (mem_req_tag),
.core_req_ready (mem_req_ready),
`UNUSED_PIN (core_req_empty),
`UNUSED_PIN (core_write_notify),
`UNUSED_PIN (core_req_wr_notify),

// Output response
.core_rsp_valid (mem_rsp_valid),
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6 changes: 3 additions & 3 deletions hw/rtl/libs/VX_mem_scheduler.sv
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ module VX_mem_scheduler #(
input wire [TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
output wire core_req_empty,
output wire core_req_sent,
output wire core_req_wr_notify,

// Core response
output wire core_rsp_valid,
Expand Down Expand Up @@ -187,8 +187,8 @@ module VX_mem_scheduler #(
// no pending requests
assign core_req_empty = !reqq_valid && ibuf_empty;

// notify request submisison
assign core_req_sent = reqq_valid && reqq_ready;
// notify write request submisison
assign core_req_wr_notify = reqq_valid && reqq_ready && reqq_rw;

// Index buffer ///////////////////////////////////////////////////////////

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