xilinx synthesis debugging foxes

configure

@@ -65,7 +65,7 @@ copy_files() {
                     filename_no_ext="${filename%.in}"
                     dest_file="$dest_dir/$filename_no_ext"
                     mkdir -p "$dest_dir"
-                    sed "s|@VORTEX_HOME@|$SCRIPT_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g" "$file" > "$dest_file"
+                    sed "s|@VORTEX_HOME@|$SCRIPT_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g; s|@CURRENTDIR@|$CURRENT_DIR|g" "$file" > "$dest_file"
                     # apply permissions to bash scripts
                     read -r firstline < "$dest_file"
                     if [[ "$firstline" =~ ^#!.*bash ]]; then

hw/rtl/VX_platform.vh

@@ -56,8 +56,25 @@
 `define UNUSED_PIN(x) . x ()
 `define UNUSED_ARG(x) x
 
+`define __SCOPE (* mark_debug="true" *)
+
+`define __SCOPE_X
+
+`define __SCOPE_ON  \
+    `undef __SCOPE_X \
+    `define __SCOPE_X `__SCOPE
+
+`define __SCOPE_OFF  \
+    `undef __SCOPE_X \
+    `define __SCOPE_X
+
 `else // not SYNTHESIS
 
+`define __SCOPE
+`define __SCOPE_X
+`define __SCOPE_ON
+`define __SCOPE_OFF
+
 `ifdef VERILATOR
 
 `ifndef TRACING_ALL

hw/rtl/afu/xrt/VX_afu_wrap.sv

@@ -21,8 +21,8 @@ module VX_afu_wrap #(
 	  parameter C_M_AXI_MEM_DATA_WIDTH  = `VX_MEM_DATA_WIDTH
 ) (
     // System signals
-    input wire ap_clk,
-    input wire ap_rst_n,
+    input wire clk,
+    input wire reset,
 
     // AXI4 master interface
 	`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
@@ -82,8 +82,6 @@ module VX_afu_wrap #(
 	// convert memory interface to array
 	`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
 
-	wire reset = ~ap_rst_n;
-
 	reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
 	reg [15:0] vx_pending_writes;
 	reg vx_busy_wait;
@@ -122,7 +120,7 @@ module VX_afu_wrap #(
 		end
 	end
 
-	always @(posedge ap_clk) begin
+	always @(posedge clk) begin
 		if (reset || ap_reset) begin
 			state             <= STATE_IDLE;
 			vx_pending_writes <= '0;
@@ -187,7 +185,7 @@ module VX_afu_wrap #(
 		.AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
 		.AXI_NUM_BANKS  (C_M_AXI_MEM_NUM_BANKS)
 	) afu_ctrl (
-		.clk       		(ap_clk),
+		.clk       		(clk),
 		.reset     		(reset),
 
 		.s_axi_awvalid  (s_axi_ctrl_awvalid),
@@ -245,7 +243,7 @@ module VX_afu_wrap #(
 	) vortex_axi (
 		`SCOPE_IO_BIND  (1)
 
-		.clk			(ap_clk),
+		.clk			(clk),
 		.reset			(vx_reset),
 
 		.m_axi_awvalid	(m_axi_mem_awvalid_a),
@@ -301,9 +299,32 @@ module VX_afu_wrap #(
 
     // SCOPE //////////////////////////////////////////////////////////////////////
 
+`ifdef CHIPSCOPE
+    ila_afu ila_afu_inst (
+      	.clk (clk),
+		.probe0 ({
+			ap_reset,
+        	ap_start,
+        	ap_done,
+			ap_idle,
+			interrupt
+		}),
+		.probe1 ({
+        	vx_pending_writes,
+			vx_busy_wait,
+			vx_busy,
+			vx_reset,
+			dcr_wr_valid,
+			dcr_wr_addr,
+			dcr_wr_data
+		})
+    );
+`endif
+
 `ifdef DBG_SCOPE_AFU
 	`define TRIGGERS { \
 		reset, \
+		ap_reset, \
 		ap_start, \
 		ap_done, \
 		ap_idle, \
@@ -343,7 +364,7 @@ module VX_afu_wrap #(
 	initial begin
 		$assertoff(0, vortex_axi);
 	end
-	always @(posedge ap_clk) begin
+	always @(posedge clk) begin
 		if (reset) begin
 			assert_delay_ctr <= '0;
 			assert_enabled   <= 0;
@@ -362,7 +383,7 @@ module VX_afu_wrap #(
 `endif
 
 `ifdef DBG_TRACE_AFU
-    always @(posedge ap_clk) begin
+    always @(posedge clk) begin
 		for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
 			if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
 				`TRACE(2, ("%t: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))

hw/rtl/afu/xrt/vortex_afu.v

@@ -1,10 +1,10 @@
 // Copyright © 2019-2023
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 // http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,12 +18,12 @@ module vortex_afu #(
 	parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
 	parameter C_M_AXI_MEM_ID_WIDTH 	  = `M_AXI_MEM_ID_WIDTH,
 	parameter C_M_AXI_MEM_ADDR_WIDTH  = 64,
-	parameter C_M_AXI_MEM_DATA_WIDTH  = `VX_MEM_DATA_WIDTH    
+	parameter C_M_AXI_MEM_DATA_WIDTH  = `VX_MEM_DATA_WIDTH
 ) (
 	// System signals
 	input wire 									ap_clk,
 	input wire 									ap_rst_n,
-	
+
 	// AXI4 master interface
 	`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
 
@@ -45,8 +45,8 @@ module vortex_afu #(
     output wire                                 s_axi_ctrl_bvalid,
     input  wire                                 s_axi_ctrl_bready,
     output wire [1:0]                           s_axi_ctrl_bresp,
-    
-    output wire                                 interrupt 
+
+    output wire                                 interrupt
 );
 
 	VX_afu_wrap #(
@@ -56,14 +56,14 @@ module vortex_afu #(
 		.C_M_AXI_MEM_ADDR_WIDTH  (C_M_AXI_MEM_ADDR_WIDTH),
 		.C_M_AXI_MEM_DATA_WIDTH  (C_M_AXI_MEM_DATA_WIDTH)
 	) afu_wrap (
-		.ap_clk             (ap_clk),
-		.ap_rst_n           (ap_rst_n),
+		.clk             	(ap_clk),
+		.reset           	(~ap_rst_n),
 
 		`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
-		
+
 		.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
 		.s_axi_ctrl_awready (s_axi_ctrl_awready),
-		.s_axi_ctrl_awaddr  (s_axi_ctrl_awaddr),		
+		.s_axi_ctrl_awaddr  (s_axi_ctrl_awaddr),
 		.s_axi_ctrl_wvalid  (s_axi_ctrl_wvalid),
 		.s_axi_ctrl_wready  (s_axi_ctrl_wready),
 		.s_axi_ctrl_wdata   (s_axi_ctrl_wdata),
@@ -81,5 +81,5 @@ module vortex_afu #(
 
 		.interrupt          (interrupt)
 	);
-	
+
 endmodule