Fixed silk designators for R1 R2 (#7)

ESP32-Zip.kicad_pcb

@@ -1,11 +1,11 @@
-(kicad_pcb (version 20171130) (host pcbnew 5.0.1)
+(kicad_pcb (version 20171130) (host pcbnew 5.1.5)
 
   (general
     (thickness 1.6)
     (drawings 37)
     (tracks 827)
     (zones 0)
-    (modules 48)
+    (modules 47)
     (nets 64)
   )
 
@@ -46,8 +46,6 @@
     (zone_clearance 0.508)
     (zone_45_only no)
     (trace_min 0.1)
-    (segment_width 0.2)
-    (edge_width 0.15)
     (via_size 0.8)
     (via_drill 0.4)
     (via_min_size 0.4)
@@ -57,6 +55,8 @@
     (uvias_allowed no)
     (uvia_min_size 0.2)
     (uvia_min_drill 0.1)
+    (edge_width 0.15)
+    (segment_width 0.2)
     (pcb_text_width 0.3)
     (pcb_text_size 1.5 1.5)
     (mod_edge_width 0.15)
@@ -1832,7 +1832,7 @@
     (tags resistor)
     (path /5C831481)
     (attr smd)
-    (fp_text reference R2 (at 0.8 -3.9 unlocked) (layer F.SilkS)
+    (fp_text reference R2 (at 0.7 1.55 unlocked) (layer F.SilkS)
       (effects (font (size 0.9 0.9) (thickness 0.15)))
     )
     (fp_text value 47.5k (at 0 1.65 180) (layer F.Fab)
@@ -1868,7 +1868,7 @@
     (tags resistor)
     (path /5C83139A)
     (attr smd)
-    (fp_text reference R1 (at -0.8 -3.8 unlocked) (layer F.SilkS)
+    (fp_text reference R1 (at -0.8 1.55 unlocked) (layer F.SilkS)
       (effects (font (size 0.9 0.9) (thickness 0.15)))
     )
     (fp_text value 22.1k (at 0 1.65) (layer F.Fab)
@@ -2777,17 +2777,6 @@
     (pad 1 thru_hole circle (at 0 0) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask))
   )
 
-  (module SwitchPanel:1.152mmHole (layer F.Cu) (tedit 5DF69FCD) (tstamp 5E4A6B6B)
-    (at 105.1 51.2)
-    (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
-      (effects (font (size 1 1) (thickness 0.15)))
-    )
-    (fp_text value 1.152mmHole (at 0 -0.5) (layer F.Fab)
-      (effects (font (size 1 1) (thickness 0.15)))
-    )
-    (pad 1 thru_hole circle (at 0 0) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask))
-  )
-
   (gr_text "For pinout see http://github.com/vintlabs/ESP32-Zip" (at 79.05 57) (layer B.SilkS)
     (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
   )
@@ -2884,7 +2873,6 @@
   (gr_line (start 49.5 80) (end 108.5 80) (layer Edge.Cuts) (width 0.15) (tstamp 5D4DDF4B))
   (gr_line (start 49.5 50) (end 108.5 50) (layer Edge.Cuts) (width 0.15))
 
-  (via (at 70.4 78.55) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 11))
   (via (at 88.6 75.6) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (via (at 93.25 75.75) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
   (via (at 95.7 72.3) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
@@ -3173,6 +3161,7 @@
   (segment (start 104.3375 59.8) (end 104.3375 61.1375) (width 0.25) (layer F.Cu) (net 9))
   (segment (start 92.9375 62) (end 92.9375 62.0375) (width 0.5) (layer F.Cu) (net 10))
   (segment (start 92.9375 61.6) (end 95.0625 61.6) (width 0.25) (layer F.Cu) (net 10))
+  (via (at 70.4 78.55) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 11))
   (via (at 63.2 74.4) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 11))
   (segment (start 63.2 74.4) (end 63.2 76.41) (width 0.25) (layer F.Cu) (net 11))
   (segment (start 63.2 76.41) (end 63.29 76.5) (width 0.25) (layer F.Cu) (net 11))

ESP32-Zip.sch

@@ -1,6 +1,5 @@
 EESchema Schematic File Version 4
-LIBS:ESP32-Zip-cache
-EELAYER 26 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -1276,4 +1275,30 @@ Wire Wire Line
 Wire Wire Line
 	5650 1850 5750 1850
 NoConn ~ 1350 3150
+$Comp
+L Device:C C?
+U 1 1 5E2B18A1
+P 2350 2350
+F 0 "C?" H 2465 2396 50  0000 L CNN
+F 1 "C" H 2465 2305 50  0000 L CNN
+F 2 "" H 2388 2200 50  0001 C CNN
+F 3 "~" H 2350 2350 50  0001 C CNN
+	1    2350 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR?
+U 1 1 5E2B1DC2
+P 2350 2500
+F 0 "#PWR?" H 2350 2250 50  0001 C CNN
+F 1 "GND" H 2355 2327 50  0000 C CNN
+F 2 "" H 2350 2500 50  0001 C CNN
+F 3 "" H 2350 2500 50  0001 C CNN
+	1    2350 2500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2350 2200 2350 2150
+Wire Wire Line
+	2350 2150 2600 2150
 $EndSCHEMATC