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simulator: Format displayed commands with quotes for multiple arguments
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Signed-off-by: Eryk Szpotanski <[email protected]>
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eszpotanski committed Jul 29, 2024
1 parent 82993eb commit 40d1826
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Showing 4 changed files with 17 additions and 5 deletions.
6 changes: 4 additions & 2 deletions src/main/scala/chiseltest/simulator/IcarusSimulator.scala
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,9 @@ private object IcarusSimulator extends Simulator with LazyLogging {
val success = ret.exitCode == 0 && os.exists(lib)
assert(
success,
s"failed to compiler VPI shared library for circuit ${topName} in work dir $compileDir\n" + cmd.mkString(" ")
s"failed to compiler VPI shared library for circuit ${topName} in work dir $compileDir\n" + Utils.quoteCmdArgs(
cmd
)
)
lib
}
Expand Down Expand Up @@ -141,7 +143,7 @@ private object IcarusSimulator extends Simulator with LazyLogging {
val ret = os.proc(cmd).call(cwd = os.pwd, check = false)

val success = ret.exitCode == 0 && os.exists(os.pwd / simBinary)
assert(success, s"iverilog command failed on circuit ${topName} in work dir $targetDir\n" + cmd.mkString(" "))
assert(success, s"iverilog command failed on circuit ${topName} in work dir $targetDir\n" + Utils.quoteCmdArgs(cmd))
Seq("vvp", simBinary.toString())
}

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9 changes: 9 additions & 0 deletions src/main/scala/chiseltest/simulator/Utils.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
// SPDX-License-Identifier: Apache-2.0

package chiseltest.simulator

object Utils {
def quoteCmdArgs(cmd: Seq[String]): String = {
cmd.map(arg => if (arg.contains(" ")) s""""$arg"""" else arg).mkString(" ")
}
}
3 changes: 2 additions & 1 deletion src/main/scala/chiseltest/simulator/VerilatorSimulator.scala
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ package chiseltest.simulator
import firrtl2._
import firrtl2.annotations._
import chiseltest.simulator.jna._
import chiseltest.simulator.Utils.quoteCmdArgs

case object VerilatorBackendAnnotation extends SimulatorAnnotation {
override def getSimulator: Simulator = VerilatorSimulator
Expand Down Expand Up @@ -219,7 +220,7 @@ private object VerilatorSimulator extends Simulator {
private def run(cmd: Seq[String], cwd: os.Path, verbose: Boolean): os.CommandResult = {
if (verbose) {
// print the command and pipe the output to stdout
println(cmd.mkString(" "))
println(quoteCmdArgs(cmd))
os.proc(cmd)
.call(cwd = cwd, stdout = os.ProcessOutput.Readlines(println), stderr = os.ProcessOutput.Readlines(println))
} else {
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Original file line number Diff line number Diff line change
Expand Up @@ -321,7 +321,7 @@ private[chiseltest] class IPCSimulatorContext(

private def start(): Unit = {
if (verbose)
println(s"""STARTING ${cmd.mkString(" ")}""")
println(s"""STARTING ${Utils.quoteCmdArgs(cmd)}""")
mwhile(!recvOutputs) {}
isRunning = true
}
Expand Down Expand Up @@ -417,7 +417,7 @@ private[chiseltest] class IPCSimulatorContext(
private object TesterProcess {
def apply(cmd: Seq[String], logs: ArrayBuffer[String], verbose: Boolean): Process = {
require(new java.io.File(cmd.head).exists, s"${cmd.head} doesn't exist")
val processBuilder = Process(cmd.mkString(" "))
val processBuilder = Process(Utils.quoteCmdArgs(cmd))
// This makes everything written to stderr get added as lines to logs
val processLogger = ProcessLogger(
{ str => if (verbose) println(str) },
Expand Down

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