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C++ output from Chisel has been dropped #738

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C++ output from Chisel has been dropped #738

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3 changes: 1 addition & 2 deletions README.md
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Expand Up @@ -10,8 +10,7 @@ language, which raises the level of hardware design abstraction by providing
concepts including object orientation, functional programming, parameterized
types, and type inference.

Chisel can generate a high-speed C++-based cycle-accurate software simulator,
or low-level Verilog designed to pass on to standard ASIC or FPGA tools
Chisel can generate low-level Verilog designed to pass on to standard ASIC or FPGA tools
for synthesis and place and route.

Visit the [community website](http://chisel.eecs.berkeley.edu/) for more
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