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Jun 6, 2020 - C
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single-port
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This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
fpga
ram
hardware
verilog
synchronous
testbench
digital-circuits
hardware-description-language
single-port
fpga-programming
memory-design
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Aug 24, 2024 - Verilog
Deploy nodejs/react app on a single port/domain.. Git repo for the corresponding medium story.
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Feb 23, 2021 - HTML
Internal Shared Functionalities for Command Line Interface Static Files Server written in TypeScript
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Sep 5, 2024 - TypeScript
Run multiple react application on a single port using nginx
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Dec 11, 2022 - TypeScript
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