Add simulation commands to example/picosoc

examples/picosoc/.gitignore

@@ -1,15 +1 @@
-/spiflash_tb.vcd
-/spiflash_tb.vvp
-/firmware.elf
-/firmware.hex
-/firmware.bin
-/hardware.asc
-/hardware.bin
-/hardware.blif
-/hardware.log
-/hardware.rpt
-/hardware_syn.v
-/hardware_syn_tb.vvp
-/hardware_tb.vvp
-/testbench.vcd
-/cmos.log
+build

examples/picosoc/Makefile

@@ -1,30 +1,51 @@
+CROSS = riscv32-unknown-elf-
+HARDWARE = hardware/*.v hardware/modules/*.v
+TESTBENCH = simulation/*.v
 
-upload: hardware.bin firmware.bin
-	tinyprog -p hardware.bin -u firmware.bin
+upload: hardware/build/hardware.bin firmware/build/firmware.bin
+	tinyprog -p hardware/build/hardware.bin -u firmware/build/firmware.bin
 
 
-hardware.blif: hardware.v spimemio.v simpleuart.v picosoc.v picorv32.v
-	yosys -ql hardware.log -p 'synth_ice40 -top hardware -blif hardware.blif' $^
+hardware/build/hardware.blif: $(HARDWARE)
+	yosys -ql hardware/build/hardware.log -p 'synth_ice40 -top hardware -blif $@' $^
 
-hardware.asc: hardware.pcf hardware.blif
-	arachne-pnr -d 8k -P cm81 -o hardware.asc -p hardware.pcf hardware.blif
+hardware/build/hardware.asc: hardware/hardware.pcf hardware/build/hardware.blif
+	arachne-pnr -d 8k -P cm81 -o $@ -p $^
 
-hardware.bin: hardware.asc
-	icetime -d hx8k -c 12 -mtr hardware.rpt hardware.asc
-	icepack hardware.asc hardware.bin
+hardware/build/hardware.bin: hardware/build/hardware.asc
+	icetime -d lp8k -c 12 -mtr hardware/build/hardware.rpt $^
+	icepack $^ $@
 
 
-firmware.elf: sections.lds start.S firmware.c 
-	riscv32-unknown-elf-gcc -march=rv32imc -nostartfiles -Wl,-Bstatic,-T,sections.lds,--strip-debug,-Map=firmware.map,--cref  -ffreestanding -nostdlib -o firmware.elf start.S firmware.c
+firmware/build/firmware.elf: firmware/sections.lds firmware/start.S firmware/firmware.c 
+	$(CROSS)gcc -march=rv32imc -mabi=ilp32 -nostartfiles -Wl,-Bstatic,-T,firmware/sections.lds,--strip-debug,-Map=firmware/firmware.map,--cref  -ffreestanding -nostdlib -o $@ firmware/start.S firmware/firmware.c
 
-firmware.bin: firmware.elf
-	riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout > firmware.bin
+firmware/build/firmware.bin: firmware/build/firmware.elf
+	$(CROSS)objcopy -O binary $^ /dev/stdout > $@
 
 
-clean:
-	rm -f firmware.elf firmware.hex firmware.bin firmware.o firmware.map \
-	      hardware.blif hardware.log hardware.asc hardware.rpt hardware.bin
+simulation/build/firmware.elf: firmware/sections.lds firmware/start.S firmware/firmware.c 
+	$(CROSS)gcc -march=rv32imc -mabi=ilp32 -nostartfiles -Wl,-Bstatic,-T,firmware/sections.lds,--strip-debug,-Map=firmware/firmware.map,--cref  -ffreestanding -nostdlib -o $@ firmware/start.S firmware/firmware.c -DSIMU
 
+simulation/build/firmware.bin: simulation/build/firmware.elf
+	$(CROSS)objcopy -O binary $^ /dev/stdout > $@
 
+simulation/build/firmware.hex: simulation/build/firmware.bin
+	xxd $^ > $@
 
+simulation/build/flash.bin: simulation/build/firmware.bin
+	simulation/zeropadding.sh $^ > $@
 
+simulation/build/flash.hex: simulation/build/flash.bin
+	xxd -c 1 -p $^ > $@
+
+simulation/build/testbench.vvp: simulation/build/flash.hex $(TESTBENCH) $(HARDWARE)
+	iverilog -s testbench -o $@ $(TESTBENCH) $(HARDWARE) `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS -DDEBUG -DDEBUGNETS -DDEBUGREGS
+
+simulation/build/testbench.vcd: simulation/build/testbench.vvp
+	vvp $^
+
+simulate: simulation/build/testbench.vcd
+	gtkwave $^
+
+.PHONY: upload simulate

examples/picosoc/firmware.c → examples/picosoc/firmware/firmware.c

@@ -31,8 +31,11 @@ void main() {
     }
 
     // switch to dual IO mode
+    // Dual IO mode is not supported by 'spiflash.v'
+#ifndef SIMU
     reg_spictrl = (reg_spictrl & ~0x007F0000) | 0x00400000;
-
+#endif 
+
     // blink the user LED
     uint32_t led_timer = 0;
 

examples/picosoc/firmware/firmware.map

@@ -0,0 +1,87 @@
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+FLASH            0x00050000         0x00100000         xr
+RAM              0x00000000         0x00002000         xrw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+
+.text           0x00050000      0x1ac
+                0x00050000                        . = ALIGN (0x4)
+ *(.text)
+ .text          0x00050000      0x13a /tmp/cck7Jikq.o
+ .text          0x0005013a       0x72 /tmp/ccLqa5rJ.o
+                0x0005013a                set_irq_mask
+                0x00050140                main
+ *(.text*)
+ *(.rodata)
+ *(.rodata*)
+ *(.srodata)
+ *(.srodata*)
+ *(.eh_frame)
+ *(.eh_frame*)
+                0x000501ac                        . = ALIGN (0x4)
+                0x000501ac                        _etext = .
+                0x000501ac                        _sidata = _etext
+
+.rela.dyn       0x000501ac        0x0
+ .rela.text     0x000501ac        0x0 /tmp/cck7Jikq.o
+
+.data           0x00000000       0x14 load address 0x000501ac
+                0x00000000                        . = ALIGN (0x4)
+                0x00000000                        _sdata = .
+                0x00000000                        _ram_start = .
+ *(.data)
+ .data          0x00000000       0x14 /tmp/cck7Jikq.o
+ .data          0x00000014        0x0 /tmp/ccLqa5rJ.o
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ *(.init_array)
+ *(.init_array*)
+                0x00000014                        . = ALIGN (0x4)
+                0x00000014                        _edata = .
+
+.bss            0x00000014        0x0 load address 0x000501c0
+                0x00000014                        . = ALIGN (0x4)
+                0x00000014                        _sbss = .
+ *(.bss)
+ .bss           0x00000014        0x0 /tmp/cck7Jikq.o
+ .bss           0x00000014        0x0 /tmp/ccLqa5rJ.o
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+                0x00000014                        . = ALIGN (0x4)
+                0x00000014                        _ebss = .
+
+.heap           0x00000014        0x0
+                0x00000014                        . = ALIGN (0x4)
+                0x00000014                        _heap_start = .
+LOAD /tmp/cck7Jikq.o
+LOAD /tmp/ccLqa5rJ.o
+OUTPUT(firmware/build/firmware.elf elf32-littleriscv)
+
+.riscv.attributes
+                0x00000000       0x2f
+ .riscv.attributes
+                0x00000000       0x2d /tmp/cck7Jikq.o
+ .riscv.attributes
+                0x0000002d       0x2f /tmp/ccLqa5rJ.o
+
+.comment        0x00000000       0x1b
+ .comment       0x00000000       0x1b /tmp/ccLqa5rJ.o
+                                 0x1c (size before relaxing)
+
+Cross Reference Table
+
+Symbol                                            File
+_ebss                                             /tmp/ccLqa5rJ.o
+_sbss                                             /tmp/ccLqa5rJ.o
+debug                                             /tmp/cck7Jikq.o
+main                                              /tmp/ccLqa5rJ.o
+                                                  /tmp/cck7Jikq.o
+set_irq_mask                                      /tmp/ccLqa5rJ.o

examples/picosoc/picosoc.v → examples/picosoc/hardware/picosoc.v

@@ -21,7 +21,7 @@
 `error "picosoc.v must be read before picorv32.v!"
 `endif
 
-`define PICORV32_REGS picosoc_regs
+// `define PICORV32_REGS picosoc_regs
 
 module picosoc (
 	input clk,

examples/picosoc/spiflash.v → examples/picosoc/simulation/spiflash.v

@@ -99,7 +99,7 @@ module spiflash (
 	reg [7:0] memory [0:16*1024*1024-1];
 
 	initial begin
-		$readmemh("firmware.hex", memory);
+		$readmemh("simulation/build/flash.hex", memory);
 	end
 
 	task spi_action;

examples/picosoc/simulation/testbench.v

@@ -0,0 +1,109 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Claire Xenia Wolf <[email protected]>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+module testbench;
+  reg clk;
+  always #5 clk = (clk === 1'b0);
+
+  localparam ser_half_period = 53;
+  event ser_sample;
+
+  initial begin
+    $dumpfile("simulation/build/testbench.vcd");
+    $dumpvars(0, testbench);
+
+    repeat (6) begin
+      repeat (50000) @(posedge clk);
+      $display("+50000 cycles");
+    end
+    $finish;
+  end
+
+  integer cycle_cnt = 0;
+
+  always @(posedge clk) begin
+    cycle_cnt <= cycle_cnt + 1;
+  end
+
+  wire led;
+
+  wire ser_rx;
+  wire ser_tx;
+
+  wire flash_csb;
+  wire flash_clk;
+  wire flash_io0;
+  wire flash_io1;
+  wire flash_io2;
+  wire flash_io3;
+
+  // always @(led) begin
+  //   #1 $display("%b", led);
+  // end
+
+  hardware hardware (
+      .clk_16mhz(clk),
+
+      .pin_1(ser_rx),
+      .pin_2(ser_tx),
+
+      .user_led(led),
+
+      .flash_csb(flash_csb),
+      .flash_clk(flash_clk),
+      .flash_io0(flash_io0),
+      .flash_io1(flash_io1),
+      .flash_io2(flash_io2),
+      .flash_io3(flash_io3)
+  );
+
+  spiflash spiflash (
+      .csb(flash_csb),
+      .clk(flash_clk),
+      .io0(flash_io0),
+      .io1(flash_io1),
+      .io2(flash_io2),
+      .io3(flash_io3)
+  );
+
+  reg [7:0] buffer;
+
+  always begin
+    @(negedge ser_tx);
+
+    repeat (ser_half_period) @(posedge clk);
+    ->ser_sample;  // start bit
+
+    repeat (8) begin
+      repeat (ser_half_period) @(posedge clk);
+      repeat (ser_half_period) @(posedge clk);
+      buffer = {ser_tx, buffer[7:1]};
+      ->ser_sample;  // data bit
+    end
+
+    repeat (ser_half_period) @(posedge clk);
+    repeat (ser_half_period) @(posedge clk);
+    ->ser_sample;  // stop bit
+
+    if (buffer < 32 || buffer >= 127) $display("Serial data: %d", buffer);
+    else $display("Serial data: '%c'", buffer);
+  end
+endmodule