[BACKPORT] fixes to SHM and CoreSPI from upstream #169
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This is a collection of tweaks / optimizations to the driver to limit CPU usage as well as interrupt processing times. The changes are as follows: - setfrequency is now no-op if the frequency does not change. Accessing MPFS_SPI_CONTROL requires synchronization to the FIC domain, which takes unnecessary time if nothing changes - load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are only tested once (instead of for every word written in loop). - Disable the RX interrupt only once (again, FIC domain access is slow) - In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the whole RX FIFO, instead of trying to read it byte-by-byte
If the vaddr resides within the user's SHM, it is a user memory mapping.
The SHM physically backed memory does not belong to the user process, but the page table containing the mapping does -> delete the page table memory regardless.
jlaitine
approved these changes
Oct 1, 2023
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