Fdt x86 arm64 #6458
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Fdt x86 arm64 #6458
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Add fundamental AARCH64 architecture FIT image support, introduce new dsc and fdf files for AARCH64 architecture, and introduce new PCD: PcdUseUniversalPayloadSerialPort to indicate which serial port component is used due to some serial port parameters are fixed for ARM SoC and Platform. Use following command to build AARCH64 UPL FIT image: " export GCC5_AARCH64_PREFIX=aarch64-linux-gnu- python UefiPayloadPkg/UniversalPayloadBuild.py -a AARCH64 -t GCC5 -b DEBUG -c UefiPayloadPkg/UefiPayloadPkg_aarch64.dsc --Fit " Signed-off-by: Amos Bu <[email protected]> Signed-off-by: Ajan Zhong <[email protected]>
Serial port and Graphic device nodes will be parsed only when 'pci-rb' node is compatible to 'pci-rb' type in current logic, this logic limits bootloader to provide informations of all Host PCI Root Bridges. However, PciHostBridgeLib library in UefiPayloadPkg provides support to scan Host PCI Root Bridges dynamically. Bootloader can utilizes Root Bridges scanning feature, and provides Serial Port and Graphic device information in a 'pci-rb' node without providing informations about all Host PCI Root Bridges. Signed-off-by: Ajan Zhong <[email protected]> refine gaphic and serial
Add Red/Green/Blue mask and pixelsperscanline properties parse when constructing GraphicInfo HoB, these properties are required during flash Framebuffer data to Graphic device. Signed-off-by: Ajan Zhong <[email protected]>
Add ARM64 support on FdtParserLib when FDT is enabled. Signed-off-by: Ajan Zhong <[email protected]>
DO NOT MERGE!!
If unaligned check has been enabled in ARM64 platform, FDT parser might dereference unaligned address to get 64-bit data. Use unaligned data read to avoid triggering unaligned data access Signed-off-by: Ajan Zhong <[email protected]>
According to ACPI Specification, 64 bit physical address of the XSDT provides indentical functionality to the RSDT but accommodates phiscal address of description headers that are larger than 32 bits. In this case physical address of XSDT table is 64 bit aligned, however size of ACPI description tabled header is not 64 bit alinged. It leads to the entry of other description headers are not 64 bit aligned. In ARM64 architecture, deference not 64 bit aligned address to get 64 bit data will trigger unaligned data access fault. Use ReadUnaligned64 method to fix this unaligned data access issue. Signed-off-by: Ajan Zhong <[email protected]>
ARM64 CpuDxe takes charge of constructing Translation tables with memory map information provided by bootloader, and enabling MMU, set correct EOIMode to adapt ARM GiC V3 implementation. Signed-off-by: Ajan Zhong <[email protected]>
SR-IOV is enabled for NVME device, it is impossible to disable controller for the first node, so we need to wait till timeout. During this timeout period, prompt message to indicate status. Signed-off-by: Ajan Zhong <[email protected]>
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