Merge branch 'master' into pg/StrSize

.github/scripts/GitHub.py

@@ -218,15 +218,17 @@ def add_reviewers_to_pr(
 
     # The current PR reviewers do not need to be requested again.
     current_pr_requested_reviewers = [
-        r.login.strip() for r in pr.get_review_requests()[0]
+        r.login.strip() for r in pr.get_review_requests()[0] if r
+    ]
+    current_pr_reviewed_reviewers = [
+        r.user.login.strip() for r in pr.get_reviews() if r and r.user
     ]
-    current_pr_reviewed_reviewers = [r.user.login.strip() for r in pr.get_reviews()]
     current_pr_reviewers = list(
         set(current_pr_requested_reviewers + current_pr_reviewed_reviewers)
     )
 
     # A user can only be added if they are a collaborator of the repository.
-    repo_collaborators = [c.login.strip() for c in repo_gh.get_collaborators()]
+    repo_collaborators = [c.login.strip() for c in repo_gh.get_collaborators() if c]
     non_collaborators = [u for u in user_names if u not in repo_collaborators]
 
     excluded_pr_reviewers = [pr_author] + current_pr_reviewers + non_collaborators
@@ -243,14 +245,15 @@ def add_reviewers_to_pr(
             # If a comment has already been made for these non-collaborators,
             # do not make another comment.
             if (
-                comment.user.login == "tianocore-assign-reviewers[bot]"
+                comment.user
+                and comment.user.login == "tianocore-assign-reviewers[bot]"
                 and "WARNING: Cannot add some reviewers" in comment.body
                 and all(u in comment.body for u in non_collaborators)
             ):
                 break
         else:
             repo_admins = [
-                a.login for a in repo_gh.get_collaborators(permission="admin")
+                a.login for a in repo_gh.get_collaborators(permission="admin") if a
             ]
 
             leave_pr_comment(

.gitmodules

@@ -1,9 +1,6 @@
 [submodule "CryptoPkg/Library/OpensslLib/openssl"]
 	path = CryptoPkg/Library/OpensslLib/openssl
 	url = https://github.com/openssl/openssl
-[submodule "SoftFloat"]
-	path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
-	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
 [submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
 	path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
 	url = https://github.com/tianocore/edk2-cmocka.git

.mailmap

@@ -38,6 +38,7 @@ Jim Dailey <[email protected]>
 Jim Dailey <[email protected]> <[email protected]>
 Laszlo Ersek <[email protected]> <lersek@6f19259b-4bc3-4df7-8a09-765794883524>
 Laszlo Ersek <[email protected]> <lersek@Edk2>
+Leif Lindholm <[email protected]> <[email protected]>
 Liming Gao <[email protected]>
 Liming Gao <[email protected]> <Gao, Liming [email protected]>
 Liming Gao <[email protected]> <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>

.pytool/CISettings.py

@@ -186,8 +186,6 @@ def GetRequiredSubmodules(self):
         If no RequiredSubmodules return an empty iterable
         '''
         rs = []
-        rs.append(RequiredSubmodule(
-            "ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3", False))
         rs.append(RequiredSubmodule(
             "CryptoPkg/Library/OpensslLib/openssl", False))
         rs.append(RequiredSubmodule(

ArmPkg/ArmPkg.ci.yaml

@@ -22,8 +22,6 @@
         ],
         ## Both file path and directory path are accepted.
         "IgnoreFiles": [
-            "Library/ArmSoftFloatLib/berkeley-softfloat-3",
-            "Library/ArmSoftFloatLib/ArmSoftFloatLib.c",
             "Universal/Smbios/SmbiosMiscDxe"
         ]
     },
@@ -90,10 +88,6 @@
     ## options defined .pytool/Plugin/SpellCheck
     "SpellCheck": {
         "AuditOnly": True,
-        "IgnoreFiles": [
-            "Library/ArmSoftFloatLib/berkeley-softfloat-3/**"
-        ],                           # use gitignore syntax to ignore errors
-                                     # in matching files
         "ExtendWords": [
           "api's",
           "ackintid",

ArmPkg/ArmPkg.dsc

@@ -91,10 +91,6 @@
 
   OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
 
-[LibraryClasses.common.SEC]
-  # ARM platforms have SEC modules with standard entry points, so we can generically link StackCheckLib
-  NULL|MdePkg/Library/StackCheckLibNull/StackCheckLibNull.inf
-
 [LibraryClasses.common.PEIM]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -144,7 +140,6 @@
   ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
   ArmPkg/Library/ArmLib/ArmBaseLib.inf
   ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
-  ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
   ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
   ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
   ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBootManagerLib.inf

ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S

@@ -9,6 +9,41 @@
 
 #include <AsmMacroLib.h>
 
+/* Special accessors for VHE */
+#define cntp_tval_el02          s3_5_c14_c2_0
+#define cntp_ctl_el02           s3_5_c14_c2_1
+#define cntp_cval_el02          s3_5_c14_c2_2
+#define cntv_tval_el02          s3_5_c14_c3_0
+#define cntv_ctl_el02           s3_5_c14_c3_1
+#define cntv_cval_el02          s3_5_c14_c3_2
+
+#define RCNT(reg, sysreg)       rvhe reg, sysreg, sysreg ## 2
+#define wCNT(sysreg, reg, tmp)  wvhe sysreg, reg, sysreg ## 2, tmp
+
+        /* Read from 'altname' when running at EL2+VHE, or 'sysreg' otherwise */
+        .macro  rvhe, reg, sysreg, altname
+        mrs     \reg, CurrentEL
+        tbz     \reg, #3, .L\@
+        mrs     \reg, hcr_el2
+        tbz     \reg, #34, .L\@   // TCR.E2H
+        mrs     \reg, \altname
+        ret
+.L\@:   mrs     \reg, \sysreg
+        ret
+        .endm
+
+        /* Write to 'altname' when running at EL2+VHE, or 'sysreg' otherwise */
+        .macro  wvhe, sysreg, reg, altname, tmp
+        mrs     \tmp, CurrentEL
+        tbz     \tmp, #3, .L\@
+        mrs     \tmp, hcr_el2
+        tbz     \tmp, #34, .L\@   // TCR.E2H
+        msr     \altname, \reg
+        ret
+.L\@:   msr     \sysreg, \reg
+        ret
+        .endm
+
 ASM_FUNC(ArmReadCntFrq)
   mrs   x0, cntfrq_el0           // Read CNTFRQ
   ret
@@ -36,68 +71,55 @@ ASM_FUNC(ArmWriteCntkCtl)
 
 
 ASM_FUNC(ArmReadCntpTval)
-  mrs   x0, cntp_tval_el0        // Read CNTP_TVAL (PL1 physical timer value register)
-  ret
+  RCNT  (x0, cntp_tval_el0)      // Read CNTP_TVAL (PL1 physical timer value register)
 
 
 ASM_FUNC(ArmWriteCntpTval)
-  msr   cntp_tval_el0, x0        // Write to CNTP_TVAL (PL1 physical timer value register)
-  ret
+  wCNT  (cntp_tval_el0, x0, x1)  // Write to CNTP_TVAL (PL1 physical timer value register)
 
 
 ASM_FUNC(ArmReadCntpCtl)
-  mrs   x0, cntp_ctl_el0         // Read CNTP_CTL (PL1 Physical Timer Control Register)
-  ret
+  RCNT  (x0, cntp_ctl_el0)       // Read CNTP_CTL (PL1 Physical Timer Control Register)
 
 
 ASM_FUNC(ArmWriteCntpCtl)
-  msr   cntp_ctl_el0, x0         // Write to  CNTP_CTL (PL1 Physical Timer Control Register)
-  ret
+  wCNT  (cntp_ctl_el0, x0, x1)   // Write to  CNTP_CTL (PL1 Physical Timer Control Register)
 
 
 ASM_FUNC(ArmReadCntvTval)
-  mrs   x0, cntv_tval_el0        // Read CNTV_TVAL (Virtual Timer Value register)
-  ret
+  RCNT  (x0, cntv_tval_el0)      // Read CNTV_TVAL (Virtual Timer Value register)
 
 
 ASM_FUNC(ArmWriteCntvTval)
-  msr   cntv_tval_el0, x0        // Write to CNTV_TVAL (Virtual Timer Value register)
-  ret
+  wCNT  (cntv_tval_el0, x0, x1) // Write to CNTV_TVAL (Virtual Timer Value register)
 
 
 ASM_FUNC(ArmReadCntvCtl)
-  mrs   x0, cntv_ctl_el0         // Read CNTV_CTL (Virtual Timer Control Register)
-  ret
+  RCNT  (x0, cntv_ctl_el0)       // Read CNTV_CTL (Virtual Timer Control Register)
 
 
 ASM_FUNC(ArmWriteCntvCtl)
-  msr   cntv_ctl_el0, x0         // Write to CNTV_CTL (Virtual Timer Control Register)
-  ret
+  wCNT  (cntv_ctl_el0, x0, x1)   // Write to CNTV_CTL (Virtual Timer Control Register)
 
 
 ASM_FUNC(ArmReadCntvCt)
   mrs  x0, cntvct_el0            // Read CNTVCT  (Virtual Count Register)
   ret
 
-
 ASM_FUNC(ArmReadCntpCval)
-  mrs   x0, cntp_cval_el0        // Read CNTP_CTVAL (Physical Timer Compare Value Register)
-  ret
+  RCNT  (x0, cntp_cval_el0)      // Read CNTP_CTVAL (Physical Timer Compare Value Register)
 
 
 ASM_FUNC(ArmWriteCntpCval)
-  msr   cntp_cval_el0, x0        // Write to CNTP_CTVAL (Physical Timer Compare Value Register)
-  ret
+  wCNT  (cntp_cval_el0, x0, x1)  // Write to CNTP_CTVAL (Physical Timer Compare Value Register)
 
 
 ASM_FUNC(ArmReadCntvCval)
-  mrs   x0, cntv_cval_el0        // Read CNTV_CTVAL (Virtual Timer Compare Value Register)
-  ret
+  RCNT  (x0, cntv_cval_el0)      // Read CNTV_CTVAL (Virtual Timer Compare Value Register)
 
 
 ASM_FUNC(ArmWriteCntvCval)
-  msr   cntv_cval_el0, x0        // write to  CNTV_CTVAL (Virtual Timer Compare Value Register)
-  ret
+  wCNT  (cntv_cval_el0, x0, x1)  // write to  CNTV_CTVAL (Virtual Timer Compare Value Register)
 
 
 ASM_FUNC(ArmReadCntvOff)

ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c

@@ -24,6 +24,23 @@
 
 STATIC  ARM_REPLACE_LIVE_TRANSLATION_ENTRY  mReplaceLiveEntryFunc = ArmReplaceLiveTranslationEntry;
 
+/**
+  Whether the current translation regime is either EL1&0 or EL2&0, and
+  therefore supports non-global, ASID-scoped memory mappings.
+ **/
+STATIC
+BOOLEAN
+TranslationRegimeIsDual (
+  VOID
+  )
+{
+  if (ArmReadCurrentEL () == AARCH64_EL2) {
+    return (ArmReadHcr () & ARM_HCR_E2H) != 0;
+  }
+
+  return TRUE;
+}
+
 STATIC
 UINT64
 ArmMemoryAttributeToPageAttribute (
@@ -39,7 +56,7 @@ ArmMemoryAttributeToPageAttribute (
 
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP:
     case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
-      if (ArmReadCurrentEL () == AARCH64_EL2) {
+      if (!TranslationRegimeIsDual ()) {
         Permissions = TT_XN_MASK;
       } else {
         Permissions = TT_UXN_MASK | TT_PXN_MASK;
@@ -53,7 +70,7 @@ ArmMemoryAttributeToPageAttribute (
 
   switch (Attributes) {
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
-      return TT_ATTR_INDX_MEMORY_WRITE_BACK;
+      return TT_ATTR_INDX_MEMORY_WRITE_BACK | Permissions;
 
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO:
@@ -65,7 +82,7 @@ ArmMemoryAttributeToPageAttribute (
 
     // Uncached and device mappings are treated as outer shareable by default,
     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-      return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+      return TT_ATTR_INDX_MEMORY_NON_CACHEABLE | Permissions;
 
     default:
       ASSERT (0);
@@ -451,7 +468,7 @@ GcdAttributeToPageAttribute (
   if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
       ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
   {
-    if (ArmReadCurrentEL () == AARCH64_EL2) {
+    if (!TranslationRegimeIsDual ()) {
       PageAttributes |= TT_XN_MASK;
     } else {
       PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;
@@ -568,6 +585,11 @@ ArmConfigureMmu (
   UINT64      TCR;
   EFI_STATUS  Status;
 
+  ASSERT (ArmReadCurrentEL () < AARCH64_EL3);
+  if (ArmReadCurrentEL () == AARCH64_EL3) {
+    return EFI_UNSUPPORTED;
+  }
+
   if (MemoryTable == NULL) {
     ASSERT (MemoryTable != NULL);
     return EFI_INVALID_PARAMETER;
@@ -589,9 +611,7 @@ ArmConfigureMmu (
   //
   // Set TCR that allows us to retrieve T0SZ in the subsequent functions
   //
-  // Ideally we will be running at EL2, but should support EL1 as well.
-  // UEFI should not run at EL3.
-  if (ArmReadCurrentEL () == AARCH64_EL2) {
+  if (!TranslationRegimeIsDual ()) {
     // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
     TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
 
@@ -617,7 +637,7 @@ ArmConfigureMmu (
       ASSERT (0); // Bigger than 48-bit memory space are not supported
       return EFI_UNSUPPORTED;
     }
-  } else if (ArmReadCurrentEL () == AARCH64_EL1) {
+  } else {
     // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
     TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
 
@@ -643,9 +663,6 @@ ArmConfigureMmu (
       ASSERT (0); // Bigger than 48-bit memory space are not supported
       return EFI_UNSUPPORTED;
     }
-  } else {
-    ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
-    return EFI_UNSUPPORTED;
   }
 
   //