Skip to content

Commit

Permalink
Update README.md
Browse files Browse the repository at this point in the history
  • Loading branch information
namgoyal authored Oct 23, 2017
1 parent 112d920 commit 67d208f
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -12,9 +12,9 @@ Table of contents
Design Doc:
-----------

To design a Simple RISC Simulator in C++.
To design a Functional and Pipeline Simulator for simple RISC processor. It takes an Assembly Program converted to Instruction MEM File in Simple RISC language, an adapted version of RISC instruction set architecture designed by Dr. Smruti Ranjan Sarangi, IIT Delhi.

For understanding Simple RISC Language refer "Computer Organisation and Architecture" book by Dr. Sarangi, IITD. Link http://www.cse.iitd.ac.in/~srsarangi/archbooksoft.html
For understanding Simple RISC Language refer "Computer Organisation and Architecture" book by Dr. Sarangi, IIT Delhi. Link http://www.cse.iitd.ac.in/~srsarangi/archbooksoft.html

FLOW DIAGRAM

Expand Down

0 comments on commit 67d208f

Please sign in to comment.