[MC6805] Add MC68HC08 variation

tgtakaoka · Dec 16, 2024 · dabe59a · dabe59a
1 parent 2f31abd
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diff --git a/README.md b/README.md
@@ -75,13 +75,13 @@ It can generate Intel HEX or Motorola S-Record output.
     libasm assembler (version 1.6.50)
     usage: asm [-o <output>] [-l <list>] <input>
       -C <CPU>          : target CPU
-         MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05 MC6809
-         HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39
-         i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
-         TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
-         HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
-         MN1610 MN1613 MN1613A J11 T11
+         MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05
+         MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039
+         i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8
+         Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650
+         F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096
+         MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002
+         NS32032 MN1610 MN1613 MN1613A J11 T11
       -o <output>       : output file
       -l <list>         : list file
       -S[<bytes>]       : output Motorola S-Record format
@@ -112,13 +112,13 @@ It can read Intel HEX or Motorola S-Record input.
     libasm disassembler (version 1.6.50)
     usage: dis -C <CPU> [-o <output>] [-l <list>] <input>
       -C <CPU>         : target CPU
-         MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05 MC6809
-         HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39
-         i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
-         TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
-         HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
-         MN1610 MN1613 MN1613A J11 T11
+         MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05
+         MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039
+         i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8
+         Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650
+         F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096
+         MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002
+         NS32032 MN1610 MN1613 MN1613A J11 T11
       -o <output>      : output file
       -l <list>        : list file
       <input>          : file can be Motorola S-Record or Intel HEX format

diff --git a/README_.adoc b/README_.adoc
@@ -79,13 +79,13 @@ It can generate Intel HEX or Motorola S-Record output.
 libasm assembler (version 1.6.50)
 usage: asm [-o <output>] [-l <list>] <input>
   -C <CPU>          : target CPU
-     MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05 MC6809
-     HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39
-     i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
-     TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
-     HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
-     MN1610 MN1613 MN1613A J11 T11
+     MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05
+     MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039
+     i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8
+     Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650
+     F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096
+     MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002
+     NS32032 MN1610 MN1613 MN1613A J11 T11
   -o <output>       : output file
   -l <list>         : list file
   -S[<bytes>]       : output Motorola S-Record format
@@ -118,13 +118,13 @@ It can read Intel HEX or Motorola S-Record input.
 libasm disassembler (version 1.6.50)
 usage: dis -C <CPU> [-o <output>] [-l <list>] <input>
   -C <CPU>         : target CPU
-     MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05 MC6809
-     HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039 i8048 i80C39
-     i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
-     TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
-     HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
-     MN1610 MN1613 MN1613A J11 T11
+     MC6800 MB8861 MC6801 HD6301 MC68HC11 MC6805 MC146805 MC68HC05
+     MC68HC08 MC6809 HD6309 MOS6502 R65C02 G65SC02 W65C02S W65C816S i8039
+     i8048 i80C39 i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8
+     Z86C Z88 TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650
+     F3850 IM6100 HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096
+     MC68000 MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002
+     NS32032 MN1610 MN1613 MN1613A J11 T11
   -o <output>      : output file
   -l <list>        : list file
   <input>          : file can be Motorola S-Record or Intel HEX format

diff --git a/src/Makefile.arch b/src/Makefile.arch
@@ -60,7 +60,7 @@ TGT_ins8060  = ins8060
 TGT_ins8070  = ins8070
 TGT_mc68000  = mc68000 mc68010 m68k m68k10
 TGT_mc6800   = mc6800 mb8861 mc6801 mc68hc11 hd6301
-TGT_mc6805   = mc68hc05
+TGT_mc6805   = mc68hc05 mc68hc08
 TGT_mc6809   = mc6809 hd6309
 TGT_mn1610   = mn1610 mn1613
 TGT_mos6502  = mos6502 g65sc02 r65c02 w65c02s w65c816
@@ -110,6 +110,7 @@ CPU_mc6800   = 6800
 CPU_mc6801   = 6801
 CPU_mc6809   = 6809
 CPU_mc68hc05 = 68HC05
+CPU_mc68hc08 = 68HC08
 CPU_mc68hc11 = 6811
 CPU_mn1610   = MN1610
 CPU_mn1613   = MN1613

diff --git a/src/asm_mc6805.cpp b/src/asm_mc6805.cpp
@@ -15,7 +15,6 @@
  */
 
 #include "asm_mc6805.h"
-
 #include "reg_mc6805.h"
 #include "table_mc6805.h"
 #include "text_common.h"
@@ -61,7 +60,7 @@ void AsmMc6805::reset() {
 }
 
 AddressWidth AsmMc6805::addressWidth() const {
-    return AddressWidth(_pc_bits == 0 ? 13 : _pc_bits);
+    return cpuType() == MC68HC08 ? ADDRESS_16BIT : AddressWidth(_pc_bits == 0 ? 13 : _pc_bits);
 }
 
 Error AsmMc6805::setPcBits(int32_t value) {
@@ -86,21 +85,27 @@ Error AsmMc6805::parseOperand(StrScanner &scan, Operand &op) const {
     }
 
     if (p.expect(',')) {
-        const auto reg = parseRegName(p);
-        if (reg == REG_X) {
+        if (parseRegName(p) == REG_X) {
             op.mode = M_IX0;
             scan = p;
             return OK;
         }
         return op.setError(scan, UNKNOWN_OPERAND);
     }
+    auto r = p;
+    if (parseRegName(r) == REG_X) {
+        op.mode = r.expect('+') ? M_IX0P : M_REGX;
+        scan = r;
+        return OK;
+    }
 
     op.size = 0;
     if (p.expect('<')) {
         op.size = 8;
     } else if (p.expect('>')) {
         op.size = 16;
     }
+    const auto disp = p;
     op.val = parseInteger(p, op);
     if (op.hasError())
         return op.getError();
@@ -109,14 +114,30 @@ Error AsmMc6805::parseOperand(StrScanner &scan, Operand &op) const {
     if (a.skipSpaces().expect(',')) {
         const auto reg = parseRegName(a.skipSpaces());
         if (reg == REG_X) {
+            const auto plus = a.expect('+');
             if (op.size == 8) {
-                op.mode = M_IDX;
+                op.mode = plus ? M_IX1P : M_IX1;
             } else if (op.size == 16) {
                 op.mode = M_IX2;
             } else if (op.val.isZero()) {
-                op.mode = M_IX0;
+                op.mode = plus ? M_IX0P : M_IX0;
+            } else if (!op.val.overflow(UINT8_MAX)) {
+                op.mode = plus ? M_IX1P : M_IX1;
             } else {
-                op.mode = op.val.overflow(UINT8_MAX) ? M_IX2 : M_IDX;
+                op.mode = M_IX2;
+            }
+            if (plus && op.mode == M_IX2)
+                return op.setError(disp, OVERFLOW_RANGE);
+            scan = a;
+            return OK;
+        }
+        if (reg == REG_SP) {
+            if (op.size == 8) {
+                op.mode = M_SP1;
+            } else if (op.size == 16) {
+                op.mode = M_SP2;
+            } else {
+                op.mode = op.val.overflow(UINT8_MAX) ? M_SP2 : M_SP1;
             }
             scan = a;
             return OK;
@@ -171,7 +192,7 @@ void AsmMc6805::emitOperand(AsmInsn &insn, AddrMode mode, const Operand &op) con
         case M_IX2:
             insn.embed(0xD0);
             goto ix2;
-        case M_IDX:
+        case M_IX1:
             insn.embed(0xE0);
             goto idx;
         default:  // M_IX0
@@ -186,7 +207,7 @@ void AsmMc6805::emitOperand(AsmInsn &insn, AddrMode mode, const Operand &op) con
         case M_BNO:
             insn.embed(0x30);
             goto dir;
-        case M_IDX:
+        case M_IX1:
             insn.embed(0x60);
             goto idx;
         default:  // M_IX0
@@ -196,13 +217,17 @@ void AsmMc6805::emitOperand(AsmInsn &insn, AddrMode mode, const Operand &op) con
         break;
     case M_DIR:
     dir:
-    case M_IDX:
+    case M_IX1:
+    case M_IX1P:
+    case M_SP1:
     idx:
         if (op.val.overflow(UINT8_MAX))
             insn.setErrorIf(op, OVERFLOW_RANGE);
         insn.emitOperand8(op.val.getUnsigned());
         break;
     case M_IX2:
+    case M_SP2:
+    case M_IM16:
     ix2:
         insn.emitOperand16(op.val.getUnsigned());
         break;
@@ -214,13 +239,19 @@ void AsmMc6805::emitOperand(AsmInsn &insn, AddrMode mode, const Operand &op) con
         break;
     case M_REL:
         return emitRelative(insn, op);
+    case M_SIM8:
+        if (op.val.overflowInt8())
+            insn.setErrorIf(op, OVERFLOW_RANGE);
+        // Fall-through
     case M_IMM:
     imm:
         if (op.val.overflowUint8())
             insn.setErrorIf(op, OVERFLOW_RANGE);
         insn.emitOperand8(op.val.getUnsigned());
         break;
-    case M_BNO:  // handled in encodeImpl(Insn)
+    case M_BNO:   // handled in encodeImpl(Insn)
+    case M_IX0P:  // silently ignore
+    case M_REGX:  // silently ignore
     default:
         break;
     }
@@ -254,6 +285,13 @@ Error AsmMc6805::encodeImpl(StrScanner &scan, Insn &_insn) const {
     return _insn.setError(insn);
 }
 
+void AsmInsn::emitInsn() {
+    uint_fast8_t pos = 0;
+    if (hasPrefix())
+        emitByte(prefix(), pos++);
+    emitByte(opCode(), pos++);
+}
+
 }  // namespace mc6805
 }  // namespace libasm
 

diff --git a/src/config_mc6805.h b/src/config_mc6805.h
@@ -26,9 +26,10 @@ enum CpuType : uint8_t {
     MC6805,
     MC146805,
     MC68HC05,
+    MC68HC08,
 };
 
-struct Config : ConfigImpl<CpuType, ADDRESS_16BIT, ADDRESS_BYTE, OPCODE_8BIT, ENDIAN_BIG, 3, 5> {
+struct Config : ConfigImpl<CpuType, ADDRESS_16BIT, ADDRESS_BYTE, OPCODE_8BIT, ENDIAN_BIG, 4, 5> {
     Config(const InsnTable<CpuType> &table) : ConfigImpl(table, MC6805) {}
 };
 

diff --git a/src/dis_mc6805.cpp b/src/dis_mc6805.cpp
@@ -15,7 +15,6 @@
  */
 
 #include "dis_mc6805.h"
-
 #include "reg_mc6805.h"
 #include "table_mc6805.h"
 
@@ -85,18 +84,22 @@ void DisMc6805::decodeExtended(DisInsn &insn, StrBuffer &out) const {
 void DisMc6805::decodeIndexed(DisInsn &insn, StrBuffer &out, AddrMode mode) const {
     if (mode == M_IX0) {
         outRegName(out.letter(','), REG_X);
-    } else if (mode == M_IX2) {
-        const uint16_t disp16 = insn.readUint16();
-        if (disp16 < 0x100)
-            out.letter('>');
-        outAbsAddr(out, disp16, ADDRESS_16BIT).letter(',');
-        outRegName(out, REG_X);
-    } else {
+    } else if (mode == M_IX0P) {
+        outRegName(out, REG_X).letter('+');
+    } else if (mode == M_IX1 || mode == M_IX1P || mode == M_SP1) {
         const uint8_t disp8 = insn.readByte();
         if (disp8 == 0)
             out.letter('<');
         outDec(out, disp8, 8).letter(',');
-        outRegName(out, REG_X);
+        outRegName(out, mode == M_SP1 ? REG_SP : REG_X);
+        if (mode == M_IX1P)
+            out.letter('+');
+    } else if (mode == M_IX2 || mode == M_SP2) {
+        const uint16_t disp16 = insn.readUint16();
+        if (disp16 < 0x100)
+            out.letter('>');
+        outAbsAddr(out, disp16, ADDRESS_16BIT).letter(',');
+        outRegName(out, mode == M_SP2 ? REG_SP : REG_X);
     }
 }
 
@@ -127,7 +130,7 @@ void DisMc6805::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) cons
             break;
         case 0x60:
         case 0xE0:
-            decodeIndexed(insn, out, M_IDX);
+            decodeIndexed(insn, out, M_IX1);
             break;
         default:
             decodeIndexed(insn, out, M_IX0);
@@ -141,18 +144,33 @@ void DisMc6805::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) cons
         break;
     case M_EXT:
         return decodeExtended(insn, out);
-    case M_IDX:
+    case M_IX1:
     case M_IX0:
     case M_IX2:
+    case M_IX0P:
+    case M_IX1P:
+    case M_SP1:
+    case M_SP2:
         decodeIndexed(insn, out, mode);
         break;
+    case M_REGX:
+        outRegName(out, REG_X);  // only for DBNZ X,rel8
+        break;
     case M_REL:
         decodeRelative(insn, out);
         break;
     case M_IMM:
         out.letter('#');
         outHex(out, insn.readByte(), 8);
         break;
+    case M_IM16:
+        out.letter('#');
+        outHex(out, insn.readUint16(), 16);
+        break;
+    case M_SIM8:
+        out.letter('#');
+        outHex(out, insn.readByte(), -8);
+        break;
     case M_BNO:
         outHex(out, (insn.opCode() >> 1) & 7, 3);
         break;
@@ -163,7 +181,14 @@ void DisMc6805::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) cons
 
 Error DisMc6805::decodeImpl(DisMemory &memory, Insn &_insn, StrBuffer &out) const {
     DisInsn insn(_insn, memory, out);
-    insn.setOpCode(insn.readByte());
+    const auto opc = insn.readByte();
+    insn.setOpCode(opc);
+    if (TABLE.isPrefix(cpuType(), opc)) {
+        insn.setPrefix(opc);
+        insn.setOpCode(insn.readByte());
+        if (insn.getError())
+            return _insn.setError(insn);
+    }
     if (TABLE.searchOpCode(cpuType(), insn, out))
         return _insn.setError(insn);