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Pipeline reset value for multi-bit signals #27

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Nov 6, 2023
Merged

Pipeline reset value for multi-bit signals #27

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c0d21f8
Set reset value for signals with bit-size greater than 1 in pipeline
lorenzschmid Nov 1, 2023
8d14ac0
Update testfiles
lorenzschmid Nov 1, 2023
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25 changes: 19 additions & 6 deletions proto/cheby/hdl/ibus.py
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
from cheby.hdltree import HDLAssign, HDLSync, HDLComment, bit_0
from cheby.hdltree import HDLAssign, HDLSync, HDLComment, HDLBinConst, bit_0
from cheby.hdl.globals import gconfig


Expand Down Expand Up @@ -77,26 +77,39 @@ def pipeline(self, root, module, conds, suffix):
# If wr_adr == rd_adr in both self and future res, do not create a signal,
# simply copy it.
continue

sig = getattr(self, n)
if sig is None or sz == 0:
# Address signals may not exist.
w = None

elif c:
w = module.new_HDLSignal(n + suffix, sz, lo)

# Reset value of pipeline
if w.size is None:
if d == 'i':
asgn = HDLAssign(w, bit_0)
else:
asgn = HDLAssign(sig, bit_0)
proc.rst_stmts.append(asgn)
cnst = bit_0
else:
cnst = HDLBinConst(0, w.size)

if d == 'i':
asgn = HDLAssign(w, cnst)
else:
asgn = HDLAssign(sig, cnst)
proc.rst_stmts.append(asgn)

# Synchronous assignment of pipeline
if d == 'i':
asgn = HDLAssign(w, sig)
else:
asgn = HDLAssign(sig, w)
proc.sync_stmts.append(asgn)

else:
w = sig

setattr(res, n, w)

if copy_wa:
res.wr_adr = res.rd_adr
module.stmts.append(proc)
Expand Down
3 changes: 3 additions & 0 deletions testfiles/bug-cernbe/repro.vhdl
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Expand Up @@ -52,7 +52,10 @@ begin
if rising_edge(Clk) then
if rst_n = '0' then
rd_ack_int <= '0';
VMERdData <= "0000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "0000000000000000";
else
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/bug-cernbe/sub_repro.vhdl
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Expand Up @@ -44,7 +44,10 @@ begin
if rising_edge(Clk) then
if rst_n = '0' then
rd_ack_int <= '0';
VMERdData <= "0000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "0000000000000000";
else
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/bug-empty/noinp.vhdl
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Expand Up @@ -94,7 +94,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/bug-empty/noout.vhdl
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Expand Up @@ -87,7 +87,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/bug-gen_wt/m1.vhdl
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Expand Up @@ -50,7 +50,10 @@ begin
if rising_edge(Clk) then
if rst_n = '0' then
rd_ack_int <= '0';
VMERdData <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
Expand Down
4 changes: 4 additions & 0 deletions testfiles/bug-memory/mem64ro.vhdl
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Expand Up @@ -103,7 +103,11 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00000000";
wr_dat_d0 <= "00000000000000000000000000000000";
wr_sel_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/bug-repmem/bran.vhdl
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Expand Up @@ -252,7 +252,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_o.dat <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0000000000000000000";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
Expand Down
4 changes: 4 additions & 0 deletions testfiles/crossbar/crossbar.v
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Expand Up @@ -91,7 +91,11 @@ module crossbar_wb
if (!wb.rst_n)
begin
rd_ack_int <= 1'b0;
wb.dati <= 32'b00000000000000000000000000000000;
wr_req_d0 <= 1'b0;
wr_adr_d0 <= 16'b0000000000000000;
wr_dat_d0 <= 32'b00000000000000000000000000000000;
wr_sel_d0 <= 32'b00000000000000000000000000000000;
end
else
begin
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/axi4_byte.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,10 @@ begin
if rising_edge(aclk) then
if areset_n = '0' then
rd_ack <= '0';
rd_data <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack <= rd_ack_d0;
rd_data <= rd_dat_d0;
Expand Down
4 changes: 4 additions & 0 deletions testfiles/features/axi4_submap_wb.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,11 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
wr_sel_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/axi4_word.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,10 @@ begin
if rising_edge(aclk) then
if areset_n = '0' then
rd_ack <= '0';
rd_data <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack <= rd_ack_d0;
rd_data <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/blkprefix1.vhdl
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Expand Up @@ -86,7 +86,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/blkprefix2.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/blkprefix3.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/blkprefix4.vhdl
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Expand Up @@ -114,7 +114,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0000";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/features/enums1.vhdl
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Expand Up @@ -76,7 +76,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/features/enums2.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/iogroup1.vhdl
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Expand Up @@ -108,7 +108,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/iogroup2.vhdl
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Expand Up @@ -95,7 +95,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/mapinfo2.vhdl
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Expand Up @@ -43,7 +43,10 @@ begin
if rising_edge(Clk) then
if rst_n = '0' then
rd_ack_int <= '0';
VMERdData <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "000000000000000000";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
VMERdData <= rd_dat_d0;
Expand Down
4 changes: 4 additions & 0 deletions testfiles/features/mem64ro.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,11 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00000000";
wr_dat_d0 <= "00000000000000000000000000000000";
wr_sel_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/features/mem64rodual.vhdl
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Expand Up @@ -95,7 +95,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_sel_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/no_port.vhdl
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Expand Up @@ -60,7 +60,10 @@ begin
if rising_edge(pclk) then
if presetn = '0' then
rd_ack <= '0';
rd_data <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack <= rd_ack_d0;
rd_data <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/features/orclrout_rw.vhdl
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Expand Up @@ -77,7 +77,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
2 changes: 2 additions & 0 deletions testfiles/features/reg-strobe.vhdl
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Expand Up @@ -78,7 +78,9 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/reg128.vhdl
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Expand Up @@ -78,7 +78,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/regprefix1.vhdl
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Expand Up @@ -94,7 +94,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/regprefix2.vhdl
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Expand Up @@ -94,7 +94,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "00";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/regprefix3.vhdl
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Expand Up @@ -90,7 +90,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0000";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/repeat-iogroup1.vhdl
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Expand Up @@ -98,7 +98,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
3 changes: 3 additions & 0 deletions testfiles/features/repeat-iogroup2.vhdl
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Expand Up @@ -102,7 +102,10 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wb_dat_o <= "00000000000000000000000000000000";
wr_req_d0 <= '0';
wr_adr_d0 <= "0";
wr_dat_d0 <= "00000000000000000000000000000000";
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
Expand Down
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