upstream

.github/workflows/release_zips.yml

@@ -10,8 +10,8 @@ jobs:
     name: Create release zip file
     runs-on: ubuntu-20.04
     steps:
-      - name: Create a recursive clone source zip
-        uses: espressif/github-actions/release_zips@master
+      - name: Create a recursive clone source and stripped zip
+        uses: Jason2866/github-actions/release_zips@release_idf
         env:
             RELEASE_PROJECT_NAME: ESP-IDF
             GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

.gitmodules

@@ -37,15 +37,6 @@
 	sbom-description = A small and fast ECDH and ECDSA implementation for 8-bit, 32-bit, and 64-bit processors
 	sbom-hash = 24c60e243580c7868f4334a1ba3123481fe1aa48
 
-[submodule "components/spiffs/spiffs"]
-	path = components/spiffs/spiffs
-	url = ../../pellepl/spiffs.git
-	sbom-version = 0.2-255-g0dbb3f71c5f6
-	sbom-supplier = Person: Peter Andersson
-	sbom-url = https://github.com/pellepl/spiffs
-	sbom-description = Wear-leveled SPI flash file system for embedded devices
-	sbom-hash = 0dbb3f71c5f6fae3747a9d935372773762baf852
-
 [submodule "components/json/cJSON"]
 	path = components/json/cJSON
 	url = ../../DaveGamble/cJSON.git

components/esp_driver_dac/dac_continuous.c

@@ -555,16 +555,17 @@ static esp_err_t s_dac_wait_to_load_dma_data(dac_continuous_handle_t handle, uin
         DAC_STAILQ_REMOVE(&handle->head, desc, lldesc_s, qe);
     }
 
-    static bool split_flag = false;
+    // TASMOTA: remove split because it does some harm and I'm not sure why it was there in the first place. No such code in 4.x
+    // static bool split_flag = false;
     uint8_t *dma_buf = (uint8_t *)desc->buf;
-    if (buf_size * DAC_16BIT_ALIGN_COEFF < 2 * handle->cfg.buf_size) {
-        if (!split_flag) {
-            buf_size >>= 1;
-            split_flag = true;
-        } else {
-            split_flag = false;
-        }
-    }
+    // if (buf_size * DAC_16BIT_ALIGN_COEFF < 2 * handle->cfg.buf_size) {
+    //     if (!split_flag) {
+    //         buf_size >>= 1;
+    //         split_flag = true;
+    //     } else {
+    //         split_flag = false;
+    //     }
+    // }
     size_t load_bytes = s_dac_load_data_into_buf(handle, dma_buf, handle->cfg.buf_size, buf, buf_size);
     lldesc_config(desc, LLDESC_HW_OWNED, 1, 0, load_bytes);
     desc->size = load_bytes;

components/esp_eth/CMakeLists.txt

@@ -34,7 +34,8 @@ if(CONFIG_ETH_ENABLED)
                          "src/phy/esp_eth_phy_ip101.c"
                          "src/phy/esp_eth_phy_ksz80xx.c"
                          "src/phy/esp_eth_phy_lan87xx.c"
-                         "src/phy/esp_eth_phy_rtl8201.c")
+                         "src/phy/esp_eth_phy_rtl8201.c"
+                         "src/phy/esp_eth_phy_jl1101.c")
     endif()
 
     if(CONFIG_ETH_SPI_ETHERNET_DM9051)

components/esp_eth/include/esp_eth_phy.h

@@ -352,6 +352,17 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config);
 */
 esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config);
 
+/**
+* @brief Create a PHY instance of JL1101
+*
+* @param[in] config: configuration of PHY
+*
+* @return
+*      - instance: create PHY instance successfully
+*      - NULL: create PHY instance failed because some error occurred
+*/
+esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config);
+
 #if CONFIG_ETH_SPI_ETHERNET_DM9051
 /**
 * @brief Create a PHY instance of DM9051

components/esp_eth/src/phy/esp_eth_phy_jl1101.c

@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_eth_phy_802_3.h"
+
+static const char *TAG = "jl1101";
+
+/***************Vendor Specific Register***************/
+
+/**
+ * @brief PSMR(Power Saving Mode Register)
+ *
+ */
+typedef union {
+    struct {
+        uint16_t reserved : 15;   /* Reserved */
+        uint16_t en_pwr_save : 1; /* Enable power saving mode */
+    };
+    uint16_t val;
+} psmr_reg_t;
+
+/**
+ * @brief PSR(Page Select Register)
+ *
+ */
+typedef union {
+    struct {
+        uint16_t page_select : 8; /* Select register page, default is 0 */
+        uint16_t reserved : 8;    /* Reserved */
+    };
+    uint16_t val;
+} psr_reg_t;
+#define ETH_PHY_PSR_REG_ADDR (0x1F)
+
+typedef struct {
+    phy_802_3_t phy_802_3;
+} phy_jl1101_t;
+
+static esp_err_t jl1101_page_select(phy_jl1101_t *jl1101, uint32_t page)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
+    psr_reg_t psr = {
+        .page_select = page
+    };
+    ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, jl1101->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed");
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_update_link_duplex_speed(phy_jl1101_t *jl1101)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
+    uint32_t addr = jl1101->phy_802_3.addr;
+    eth_speed_t speed = ETH_SPEED_10M;
+    eth_duplex_t duplex = ETH_DUPLEX_HALF;
+    bmcr_reg_t bmcr;
+    bmsr_reg_t bmsr;
+    uint32_t peer_pause_ability = false;
+    anlpar_reg_t anlpar;
+    ESP_GOTO_ON_ERROR(jl1101_page_select(jl1101, 0), err, TAG, "select page 0 failed");
+    ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
+    ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
+    eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
+    /* check if link status changed */
+    if (jl1101->phy_802_3.link_status != link) {
+        /* when link up, read negotiation result */
+        if (link == ETH_LINK_UP) {
+            ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+            if (bmcr.speed_select) {
+                speed = ETH_SPEED_100M;
+            } else {
+                speed = ETH_SPEED_10M;
+            }
+            if (bmcr.duplex_mode) {
+                duplex = ETH_DUPLEX_FULL;
+            } else {
+                duplex = ETH_DUPLEX_HALF;
+            }
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
+            /* if we're in duplex mode, and peer has the flow control ability */
+            if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
+                peer_pause_ability = 1;
+            } else {
+                peer_pause_ability = 0;
+            }
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
+        }
+        ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
+        jl1101->phy_802_3.link_status = link;
+    }
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_get_link(esp_eth_phy_t *phy)
+{
+    esp_err_t ret = ESP_OK;
+    phy_jl1101_t *jl1101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_jl1101_t, phy_802_3);
+    /* Updata information about link, speed, duplex */
+    ESP_GOTO_ON_ERROR(jl1101_update_link_duplex_speed(jl1101), err, TAG, "update link duplex speed failed");
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+    esp_eth_mediator_t *eth = phy_802_3->eth;
+    if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
+        bmcr_reg_t bmcr;
+        ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+        ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
+    }
+    return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_loopback(esp_eth_phy_t *phy, bool enable)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+    bool auto_nego_en;
+    ESP_GOTO_ON_ERROR(jl1101_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
+    ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
+    return esp_eth_phy_802_3_loopback(phy_802_3, enable);
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_init(esp_eth_phy_t *phy)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+
+    /* Basic PHY init */
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
+
+    /* Check PHY ID */
+    uint32_t oui;
+    uint8_t model;
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
+    ESP_GOTO_ON_FALSE(oui == 0x24DF10 && model == 0x2, ESP_FAIL, err, TAG, "wrong chip ID");
+
+    return ESP_OK;
+err:
+    return ret;
+}
+
+esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config)
+{
+    esp_eth_phy_t *ret = NULL;
+    phy_jl1101_t *jl1101 = calloc(1, sizeof(phy_jl1101_t));
+    ESP_GOTO_ON_FALSE(jl1101, NULL, err, TAG, "calloc jl1101 failed");
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&jl1101->phy_802_3, config) == ESP_OK,
+                        NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
+
+    // redefine functions which need to be customized for sake of jl1101
+    jl1101->phy_802_3.parent.init = jl1101_init;
+    jl1101->phy_802_3.parent.get_link = jl1101_get_link;
+    jl1101->phy_802_3.parent.autonego_ctrl = jl1101_autonego_ctrl;
+    jl1101->phy_802_3.parent.loopback = jl1101_loopback;
+
+    return &jl1101->phy_802_3.parent;
+err:
+    if (jl1101 != NULL) {
+        free(jl1101);
+    }
+    return ret;
+}

components/esp_hw_support/mac_addr.c

@@ -287,6 +287,8 @@ static esp_err_t get_efuse_factory_mac(uint8_t *mac)
         uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5];
         if (((mac_high & 0xFFFF) == 0x18fe) && (mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
             return ESP_OK;
+        } else if (esp_efuse_get_pkg_ver() ==  3) {
+            return ESP_OK;  // override for Xiaomi SOC's and maybe others too
         } else {
             ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
 #ifdef CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR

components/esp_psram/esp32/esp_psram_impl_quad.c

@@ -866,7 +866,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void)   //psram init
         psram_io.psram_cs_io  = D2WD_PSRAM_CS_IO;
     } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
         ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
-        abort();
+        return ESP_FAIL;
     } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
         ESP_EARLY_LOGI(TAG, "This chip is %s",
                        (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) ? "ESP32-PICO" : "ESP32-U4WDH");
@@ -903,7 +903,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void)   //psram init
         psram_io.psram_cs_io  = D0WDR2_V3_PSRAM_CS_IO;
     } else {
         ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %" PRIu32, pkg_ver);
-        abort();
+        return ESP_FAIL;
     }
     s_psram_cs_io = psram_io.psram_cs_io;
 

components/hal/esp32p4/include/hal/i2c_ll.h

@@ -150,6 +150,7 @@ static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
 #define i2c_ll_enable_bus_clock(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_enable_bus_clock(__VA_ARGS__);} while(0)
 
 /**
@@ -170,6 +171,7 @@ static inline void i2c_ll_reset_register(int i2c_port)
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
 #define i2c_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_reset_register(__VA_ARGS__);} while(0)
 
 /**
@@ -796,6 +798,7 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
 #define i2c_ll_set_source_clk(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_set_source_clk(__VA_ARGS__);} while(0)
 
 /**

components/hal/esp32p4/include/hal/uart_ll.h

@@ -478,6 +478,7 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
  */
 FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
 {
+int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
 #define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
     const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
     uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
@@ -507,7 +508,7 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
 }
 #if !BOOTLOADER_BUILD
 //HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
-#define uart_ll_set_baudrate(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__)
+#define uart_ll_set_baudrate(...)
 #endif
 
 /**

components/soc/esp32c2/include/soc/soc.h

@@ -30,7 +30,7 @@
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{

components/soc/esp32c3/include/soc/soc.h

@@ -23,7 +23,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on C3
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000)))    // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{

components/soc/esp32c6/include/soc/soc.h

@@ -23,7 +23,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI on C6
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000)))    // only one GPSPI on C6
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE)                    // only one I2C on C6
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE)                      // only one MCPWM on C6
 #define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x2000)       // TWAI0 and TWAI1

components/soc/esp32h2/include/soc/soc.h

@@ -23,7 +23,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on H2
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI
+#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i - 2) * 0x1000)   // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
 
 //Registers Operation {{

components/soc/esp32s2/include/soc/soc.h

@@ -25,7 +25,7 @@
 #define REG_I2S_BASE( i )       (DR_REG_I2S_BASE)
 #define REG_TIMG_BASE(i)        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define REG_SPI_BASE(i)         (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))    // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Convenient way to replace the register ops when ulp riscv projects

components/soc/esp32s3/include/soc/soc.h

@@ -34,7 +34,7 @@
 #define REG_I2S_BASE( i )       (DR_REG_I2S_BASE + (i) * 0x1E000)
 #define REG_TIMG_BASE(i)        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define REG_SPI_BASE(i)         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Convenient way to replace the register ops when ulp riscv projects