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* Create package.json
* Create version.txt
* Update entity.py
* Delete components/wifi_provisioning directory
* Update install.sh
* add jl1101
* Update dac_continuous.c
* Update mac_addr.c
* Update esp_psram_impl_quad.c
* Update Kconfig
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Jason2866 authored Jul 2, 2024
1 parent a23f078 commit 01c738d
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Showing 55 changed files with 252 additions and 8,495 deletions.
4 changes: 2 additions & 2 deletions .github/workflows/release_zips.yml
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ jobs:
name: Create release zip file
runs-on: ubuntu-20.04
steps:
- name: Create a recursive clone source zip
uses: espressif/github-actions/release_zips@master
- name: Create a recursive clone source and stripped zip
uses: Jason2866/github-actions/release_zips@release_idf
env:
RELEASE_PROJECT_NAME: ESP-IDF
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
19 changes: 10 additions & 9 deletions components/driver/dac/dac_continuous.c
Original file line number Diff line number Diff line change
Expand Up @@ -556,16 +556,17 @@ static esp_err_t s_dac_wait_to_load_dma_data(dac_continuous_handle_t handle, uin
DAC_STAILQ_REMOVE(&handle->head, desc, lldesc_s, qe);
}

static bool split_flag = false;
// TASMOTA: remove split because it does some harm and I'm not sure why it was there in the first place. No such code in 4.x
// static bool split_flag = false;
uint8_t *dma_buf = (uint8_t *)desc->buf;
if (buf_size * DAC_16BIT_ALIGN_COEFF < 2 * handle->cfg.buf_size) {
if (!split_flag) {
buf_size >>= 1;
split_flag = true;
} else {
split_flag = false;
}
}
// if (buf_size * DAC_16BIT_ALIGN_COEFF < 2 * handle->cfg.buf_size) {
// if (!split_flag) {
// buf_size >>= 1;
// split_flag = true;
// } else {
// split_flag = false;
// }
// }
size_t load_bytes = s_dac_load_data_into_buf(handle, dma_buf, handle->cfg.buf_size, buf, buf_size);
lldesc_config(desc, LLDESC_HW_OWNED, 1, 0, load_bytes);
desc->size = load_bytes;
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3 changes: 2 additions & 1 deletion components/esp_eth/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,8 @@ if(CONFIG_ETH_ENABLED)
"src/esp_eth_phy_ip101.c"
"src/esp_eth_phy_ksz80xx.c"
"src/esp_eth_phy_lan87xx.c"
"src/esp_eth_phy_rtl8201.c")
"src/esp_eth_phy_rtl8201.c"
"src/esp_eth_phy_jl1101.c")
endif()

if(CONFIG_ETH_SPI_ETHERNET_DM9051)
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11 changes: 11 additions & 0 deletions components/esp_eth/include/esp_eth_phy.h
Original file line number Diff line number Diff line change
Expand Up @@ -352,6 +352,17 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config);
*/
esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config);

/**
* @brief Create a PHY instance of JL1101
*
* @param[in] config: configuration of PHY
*
* @return
* - instance: create PHY instance successfully
* - NULL: create PHY instance failed because some error occurred
*/
esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config);

#if CONFIG_ETH_SPI_ETHERNET_DM9051
/**
* @brief Create a PHY instance of DM9051
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186 changes: 186 additions & 0 deletions components/esp_eth/src/esp_eth_phy_jl1101.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,186 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <string.h>
#include <stdlib.h>
#include <sys/cdefs.h>
#include "esp_log.h"
#include "esp_check.h"
#include "esp_eth_phy_802_3.h"

static const char *TAG = "jl1101";

/***************Vendor Specific Register***************/

/**
* @brief PSMR(Power Saving Mode Register)
*
*/
typedef union {
struct {
uint16_t reserved : 15; /* Reserved */
uint16_t en_pwr_save : 1; /* Enable power saving mode */
};
uint16_t val;
} psmr_reg_t;

/**
* @brief PSR(Page Select Register)
*
*/
typedef union {
struct {
uint16_t page_select : 8; /* Select register page, default is 0 */
uint16_t reserved : 8; /* Reserved */
};
uint16_t val;
} psr_reg_t;
#define ETH_PHY_PSR_REG_ADDR (0x1F)

typedef struct {
phy_802_3_t phy_802_3;
} phy_jl1101_t;

static esp_err_t jl1101_page_select(phy_jl1101_t *jl1101, uint32_t page)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
psr_reg_t psr = {
.page_select = page
};
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, jl1101->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed");
return ESP_OK;
err:
return ret;
}

static esp_err_t jl1101_update_link_duplex_speed(phy_jl1101_t *jl1101)
{
esp_err_t ret = ESP_OK;
esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
uint32_t addr = jl1101->phy_802_3.addr;
eth_speed_t speed = ETH_SPEED_10M;
eth_duplex_t duplex = ETH_DUPLEX_HALF;
bmcr_reg_t bmcr;
bmsr_reg_t bmsr;
uint32_t peer_pause_ability = false;
anlpar_reg_t anlpar;
ESP_GOTO_ON_ERROR(jl1101_page_select(jl1101, 0), err, TAG, "select page 0 failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
/* check if link status changed */
if (jl1101->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
if (bmcr.speed_select) {
speed = ETH_SPEED_100M;
} else {
speed = ETH_SPEED_10M;
}
if (bmcr.duplex_mode) {
duplex = ETH_DUPLEX_FULL;
} else {
duplex = ETH_DUPLEX_HALF;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
peer_pause_ability = 1;
} else {
peer_pause_ability = 0;
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
}
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
jl1101->phy_802_3.link_status = link;
}
return ESP_OK;
err:
return ret;
}

static esp_err_t jl1101_get_link(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_jl1101_t *jl1101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_jl1101_t, phy_802_3);
/* Updata information about link, speed, duplex */
ESP_GOTO_ON_ERROR(jl1101_update_link_duplex_speed(jl1101), err, TAG, "update link duplex speed failed");
return ESP_OK;
err:
return ret;
}

static esp_err_t jl1101_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
esp_eth_mediator_t *eth = phy_802_3->eth;
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
bmcr_reg_t bmcr;
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
}
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
err:
return ret;
}

static esp_err_t jl1101_loopback(esp_eth_phy_t *phy, bool enable)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
bool auto_nego_en;
ESP_GOTO_ON_ERROR(jl1101_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
err:
return ret;
}

static esp_err_t jl1101_init(esp_eth_phy_t *phy)
{
esp_err_t ret = ESP_OK;
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);

/* Basic PHY init */
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");

/* Check PHY ID */
uint32_t oui;
uint8_t model;
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
ESP_GOTO_ON_FALSE(oui == 0x24DF10 && model == 0x2, ESP_FAIL, err, TAG, "wrong chip ID");

return ESP_OK;
err:
return ret;
}

esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config)
{
esp_eth_phy_t *ret = NULL;
phy_jl1101_t *jl1101 = calloc(1, sizeof(phy_jl1101_t));
ESP_GOTO_ON_FALSE(jl1101, NULL, err, TAG, "calloc jl1101 failed");
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&jl1101->phy_802_3, config) == ESP_OK,
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");

// redefine functions which need to be customized for sake of jl1101
jl1101->phy_802_3.parent.init = jl1101_init;
jl1101->phy_802_3.parent.get_link = jl1101_get_link;
jl1101->phy_802_3.parent.autonego_ctrl = jl1101_autonego_ctrl;
jl1101->phy_802_3.parent.loopback = jl1101_loopback;

return &jl1101->phy_802_3.parent;
err:
if (jl1101 != NULL) {
free(jl1101);
}
return ret;
}
2 changes: 2 additions & 0 deletions components/esp_hw_support/mac_addr.c
Original file line number Diff line number Diff line change
Expand Up @@ -286,6 +286,8 @@ static esp_err_t get_efuse_factory_mac(uint8_t *mac)
uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5];
if (((mac_high & 0xFFFF) == 0x18fe) && (mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
return ESP_OK;
} else if (esp_efuse_get_pkg_ver() == 3) {
return ESP_OK; // override for Xiaomi SOC's and maybe others too
} else {
ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
#ifdef CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR
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4 changes: 2 additions & 2 deletions components/esp_psram/esp32/esp_psram_impl_quad.c
Original file line number Diff line number Diff line change
Expand Up @@ -866,7 +866,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
abort();
return ESP_FAIL;
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
ESP_EARLY_LOGI(TAG, "This chip is %s",
(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) ? "ESP32-PICO" : "ESP32-U4WDH");
Expand Down Expand Up @@ -903,7 +903,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
} else {
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
abort();
return ESP_FAIL;
}
s_psram_cs_io = psram_io.psram_cs_io;

Expand Down
14 changes: 3 additions & 11 deletions components/esp_wifi/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -281,7 +281,7 @@ menu "Wi-Fi"
config ESP_WIFI_ENABLE_WPA3_SAE
bool "Enable WPA3-Personal"
default y
select ESP_WIFI_MBEDTLS_CRYPTO
depends on ESP_WIFI_MBEDTLS_CRYPTO
help
Select this option to allow the device to establish a WPA3-Personal connection with eligible AP's.
PMF (Protected Management Frames) is a prerequisite feature for a WPA3 connection, it needs to be
Expand Down Expand Up @@ -465,16 +465,9 @@ menu "Wi-Fi"
select MBEDTLS_ECP_C
select MBEDTLS_ECDH_C
select MBEDTLS_ECDSA_C
select MBEDTLS_CMAC_C
select MBEDTLS_ECP_DP_SECP256R1_ENABLED
select MBEDTLS_TLS_ENABLED
help
Select this option to enable the use of MbedTLS crypto APIs.
The internal crypto support within the supplicant is limited
and may not suffice for all new security features, including WPA3.

It is recommended to always keep this option enabled. Additionally,
note that MbedTLS can leverage hardware acceleration if available,
resulting in significantly faster cryptographic operations.
Select this option to use MbedTLS crypto APIs which utilize hardware acceleration.

if ESP_WIFI_MBEDTLS_CRYPTO
config ESP_WIFI_MBEDTLS_TLS_CLIENT
Expand All @@ -501,7 +494,6 @@ menu "Wi-Fi"
config ESP_WIFI_SUITE_B_192
bool "Enable NSA suite B support with 192 bit key"
default n
depends on SOC_WIFI_GCMP_SUPPORT
select ESP_WIFI_GCMP_SUPPORT
select ESP_WIFI_GMAC_SUPPORT
help
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2 changes: 1 addition & 1 deletion components/soc/esp32c2/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )

//Registers Operation {{
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2 changes: 1 addition & 1 deletion components/soc/esp32c3/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )

//Registers Operation {{
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2 changes: 1 addition & 1 deletion components/soc/esp32c6/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI on C6
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
Expand Down
2 changes: 1 addition & 1 deletion components/soc/esp32h2/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)

//Registers Operation {{
Expand Down
2 changes: 1 addition & 1 deletion components/soc/esp32s2/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )

//Convenient way to replace the register ops when ulp riscv projects
Expand Down
2 changes: 1 addition & 1 deletion components/soc/esp32s3/include/soc/soc.h
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )

//Convenient way to replace the register ops when ulp riscv projects
Expand Down
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