Merge pull request #113 from system76/darp10-gpio

Use gpio to detect darp10/darp10-b
system76 · Jun 20, 2024 · bb1fee3 · bb1fee3
2 parents e067f3d + 1f61bbc
commit bb1fee3
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Showing 3 changed files with 68 additions and 6 deletions.
diff --git a/src/app/ec.rs b/src/app/ec.rs
@@ -18,7 +18,7 @@ use std::{
     str,
 };
 
-use super::{pci_read, shell, Component, EC2ROM, ECROM, ECTAG, FIRMWAREDIR, FIRMWARENSH};
+use super::{pci_read, shell, Component, EC2ROM, ECROM, ECTAG, FIRMWAREDIR, FIRMWARENSH, sideband::Sideband};
 
 pub struct UefiTimeout {
     duration: u64,
@@ -280,11 +280,14 @@ impl EcComponent {
                 "NS50_70PU" => "system76/darp8".to_string(),
                 "NS50_70AU" => "system76/darp9".to_string(),
                 "V5x0TU" => {
-                    // If the EC version starts with 1.07. then this is the 16 inch variant
-                    if self.version.starts_with("1.07.") {
-                        "system76/darp10".to_string()
-                    } else {
-                        "system76/darp10-b".to_string()
+                    // If GPP_E2 is high, this is the 16 inch variant
+                    unsafe {
+                        let sideband = Sideband::new(0xE000_0000);
+                        if sideband.gpio(0xD2, 0x36) & 2 == 2 {
+                            "system76/darp10-b".to_string()
+                        } else {
+                            "system76/darp10".to_string()
+                        }
                     }
                 },
                 "NV40Mx" | "NV40Mx-DV" | "NV40MJ" => "system76/galp5".to_string(),

diff --git a/src/app/mod.rs b/src/app/mod.rs
@@ -34,6 +34,7 @@ mod component;
 mod ec;
 mod mapper;
 mod pci;
+mod sideband;
 
 static ECROM: &str = concat!("\\", env!("BASEDIR"), "\\firmware\\ec.rom");
 static ECTAG: &str = concat!("\\", env!("BASEDIR"), "\\firmware\\ec.tag");

diff --git a/src/app/sideband.rs b/src/app/sideband.rs
@@ -0,0 +1,58 @@
+// Copyright 2018-2021 System76 <[email protected]>
+//
+// SPDX-License-Identifier: GPL-3.0-only
+
+use core::ptr;
+
+// P2SB private registers.
+const P2SB_PORTID_SHIFT: u32 = 16;
+
+// GPIO sideband registers.
+const REG_PCH_GPIO_PADBAR: u32 = 0xc;
+
+pub struct Sideband {
+    pub addr: u64,
+}
+
+impl Sideband {
+    pub unsafe fn new(sbreg_phys: usize) -> Self {
+        // On UEFI, physical memory is identity mapped
+        Self { addr: sbreg_phys as u64 }
+    }
+
+    #[must_use]
+    pub unsafe fn read(&self, port: u8, reg: u32) -> u32 {
+        let offset = (u64::from(port) << P2SB_PORTID_SHIFT) + u64::from(reg);
+        if offset < 1 << 24 {
+            let addr = self.addr + offset;
+            ptr::read(addr as *mut u32)
+        } else {
+            0
+        }
+    }
+
+    pub unsafe fn write(&self, port: u8, reg: u32, value: u32) {
+        let offset = (u64::from(port) << P2SB_PORTID_SHIFT) + u64::from(reg);
+        if offset < 1 << 24 {
+            let addr = self.addr + offset;
+            ptr::write(addr as *mut u32, value);
+        }
+    }
+
+    #[must_use]
+    pub unsafe fn gpio(&self, port: u8, pad: u8) -> u64 {
+        let padbar: u32 = self.read(port, REG_PCH_GPIO_PADBAR);
+
+        let dw1: u32 = self.read(port, padbar + u32::from(pad) * 8 + 4);
+        let dw0: u32 = self.read(port, padbar + u32::from(pad) * 8);
+
+        u64::from(dw0) | u64::from(dw1) << 32
+    }
+
+    pub unsafe fn set_gpio(&self, port: u8, pad: u8, value: u64) {
+        let padbar: u32 = self.read(port, REG_PCH_GPIO_PADBAR);
+
+        self.write(port, padbar + u32::from(pad) * 8 + 4, (value >> 32) as u32);
+        self.write(port, padbar + u32::from(pad) * 8, value as u32);
+    }
+}