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Gem5-RISC-V-Duel-Atomic-Timing-Benchmark-Insights
Gem5-RISC-V-Duel-Atomic-Timing-Benchmark-Insights PublicThe primary goal of the project is to systematically generate and analyze benchmark suites for the RISC-V Instruction Set Architecture using the riscv-gnu-toolchain.
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Fibonacci-Series-generator
Fibonacci-Series-generator PublicDesigned a 4-bit Fibonacci Series generator with both asynchronous reset and synchronous reset in Verilog using an adder and two registers.Modified the design by using hierarchical Approach and tes…
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