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Update for new pac
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@usbalbin
usbalbin committed Dec 5, 2024
1 parent d13db0c commit afd5dfa
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Showing 46 changed files with 1,697 additions and 1,530 deletions.
3 changes: 2 additions & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,8 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] }
embedded-dma = "0.2.0"
cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
defmt = { version = ">=0.2.0,<0.4", optional = true }
stm32h7 = { version = "^0.15.1", default-features = false }
#stm32h7 = { version = "^0.15.1", default-features = false }
stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", default-features = false }
void = { version = "1.0.2", default-features = false }
cast = { version = "0.3.0", default-features = false }
nb = "1.0.0"
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170 changes: 89 additions & 81 deletions src/adc.rs
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19 changes: 10 additions & 9 deletions src/can.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -94,15 +94,15 @@ macro_rules! message_ram_layout {
let mut word_adr: u16 = $start_word_addr;

// 11-bit filter
$can.sidfc
$can.sidfc()
.modify(|_, w| unsafe { w.flssa().bits(word_adr) });
word_adr += STANDARD_FILTER_MAX as u16;
// 29-bit filter
$can.xidfc
$can.xidfc()
.modify(|_, w| unsafe { w.flesa().bits(word_adr) });
word_adr += 2 * EXTENDED_FILTER_MAX as u16;
// Rx FIFO 0
$can.rxf0c.modify(|_, w| unsafe {
$can.rxf0c().modify(|_, w| unsafe {
w.f0sa()
.bits(word_adr)
.f0s()
Expand All @@ -112,7 +112,7 @@ macro_rules! message_ram_layout {
});
word_adr += 18 * RX_FIFO_MAX as u16;
// Rx FIFO 1
$can.rxf1c.modify(|_, w| unsafe {
$can.rxf1c().modify(|_, w| unsafe {
w.f1sa()
.bits(word_adr)
.f1s()
Expand All @@ -123,7 +123,7 @@ macro_rules! message_ram_layout {
word_adr += 18 * RX_FIFO_MAX as u16;
// Rx buffer - see below
// Tx event FIFO
$can.txefc.modify(|_, w| unsafe {
$can.txefc().modify(|_, w| unsafe {
w.efsa()
.bits(word_adr)
.efs()
Expand All @@ -133,22 +133,23 @@ macro_rules! message_ram_layout {
});
word_adr += 2 * TX_EVENT_MAX as u16;
// Tx buffers
$can.txbc.modify(|_, w| unsafe {
$can.txbc().modify(|_, w| unsafe {
w.tbsa().bits(word_adr).tfqs().bits(TX_FIFO_MAX)
});
word_adr += 18 * TX_FIFO_MAX as u16;

// Rx Buffer - not used
$can.rxbc.modify(|_, w| unsafe { w.rbsa().bits(word_adr) });
$can.rxbc()
.modify(|_, w| unsafe { w.rbsa().bits(word_adr) });

// TX event FIFO?
// Trigger memory?

// Set the element sizes to 16 bytes
$can.rxesc.modify(|_, w| unsafe {
$can.rxesc().modify(|_, w| unsafe {
w.rbds().bits(0b111).f1ds().bits(0b111).f0ds().bits(0b111)
});
$can.txesc.modify(|_, w| unsafe { w.tbds().bits(0b111) });
$can.txesc().modify(|_, w| unsafe { w.tbds().bits(0b111) });
};
}

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49 changes: 31 additions & 18 deletions src/crc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,8 @@ impl Crc {

// manual says unit must be reset (or DR read) before change of polynomial
// (technically only in case of ongoing calculation, but DR is buffered)
self.reg.cr.modify(|_, w| {
//NOTE(unsafe) Only valid bit patterns are written
self.reg.cr().modify(|_, w| unsafe {
w.polysize()
.bits(config.poly.polysize())
.rev_in()
Expand All @@ -47,8 +48,14 @@ impl Crc {
.reset()
.set_bit()
});
self.reg.pol.write(|w| w.pol().bits(config.poly.pol()));
self.reg.init.write(|w| w.init().bits(config.initial));
//NOTE(unsafe) All bit patterns are valid
self.reg
.pol()
.write(|w| unsafe { w.pol().bits(config.poly.pol()) });
//NOTE(unsafe) All bit patterns are valid
self.reg
.init()
.write(|w| unsafe { w.init().bits(config.initial) });
// writing to INIT sets DR to its value
}

Expand All @@ -60,18 +67,23 @@ impl Crc {
let mut words = data.chunks_exact(4);
for word in words.by_ref() {
let word = u32::from_be_bytes(word.try_into().unwrap());
self.reg.dr().write(|w| w.dr().bits(word));
//NOTE(unsafe) All bit patterns are valid
self.reg.dr().write(|w| unsafe { w.dr().bits(word) });
}

// there will be at most 3 bytes remaining, so 1 half-word and 1 byte
let mut half_word = words.remainder().chunks_exact(2);
if let Some(half_word) = half_word.next() {
let half_word = u16::from_be_bytes(half_word.try_into().unwrap());
self.reg.dr16().write(|w| w.dr16().bits(half_word));
//NOTE(unsafe) All bit patterns are valid
self.reg
.dr16()
.write(|w| unsafe { w.dr16().bits(half_word) });
}

if let Some(byte) = half_word.remainder().first() {
self.reg.dr8().write(|w| w.dr8().bits(*byte));
//NOTE(unsafe) All bit patterns are valid
self.reg.dr8().write(|w| unsafe { w.dr8().bits(*byte) });
}
}

Expand All @@ -87,7 +99,7 @@ impl Crc {
/// This does not reset the configuration options.
pub fn finish(&mut self) -> u32 {
let result = self.read_crc();
self.reg.cr.modify(|_, w| w.reset().set_bit());
self.reg.cr().modify(|_, w| w.reset().set_bit());
result
}

Expand All @@ -105,7 +117,7 @@ impl Crc {
/// algorithm that does not apply an output XOR or reverse the output bits.
pub fn read_state(&self) -> u32 {
let state = self.read_crc_no_xor();
if self.reg.cr.read().rev_out().is_reversed() {
if self.reg.cr().read().rev_out().is_reversed() {
state.reverse_bits()
} else {
state
Expand All @@ -123,14 +135,15 @@ impl Crc {
///
/// The IDR is not involved with CRC calculation.
pub fn set_idr(&mut self, value: u32) {
self.reg.idr.write(|w| w.idr().bits(value));
//NOTE(unsafe) All bit patterns are valid
self.reg.idr().write(|w| unsafe { w.idr().bits(value) });
}

/// Get the current value of the independent data register.
///
/// The IDR is not involved with CRC calculation.
pub fn get_idr(&self) -> u32 {
self.reg.idr.read().idr().bits()
self.reg.idr().read().idr().bits()
}

/// Returns a reference to the inner peripheral
Expand Down Expand Up @@ -226,10 +239,10 @@ impl Polynomial {
/// Return POLYSIZE register value.
const fn polysize(self) -> u8 {
(match self.0 {
Poly::B7(_) => crc::cr::POLYSIZE_A::Polysize7,
Poly::B8(_) => crc::cr::POLYSIZE_A::Polysize8,
Poly::B16(_) => crc::cr::POLYSIZE_A::Polysize16,
Poly::B32(_) => crc::cr::POLYSIZE_A::Polysize32,
Poly::B7(_) => crc::cr::POLYSIZE::Polysize7,
Poly::B8(_) => crc::cr::POLYSIZE::Polysize8,
Poly::B16(_) => crc::cr::POLYSIZE::Polysize16,
Poly::B32(_) => crc::cr::POLYSIZE::Polysize32,
}) as u8
}

Expand Down Expand Up @@ -307,11 +320,11 @@ enum Poly {
#[repr(u8)]
pub enum BitReversal {
/// Each input byte has its bits reversed. `0x1A2B3C4D` becomes `0x58D43CB2`.
Byte = crc::cr::REV_IN_A::Byte as u8,
Byte = crc::cr::REV_IN::Byte as u8,
/// Bits reversed by half-word. `0x1A2B3C4D` becomes `0xD458B23C`.
HalfWord = crc::cr::REV_IN_A::HalfWord as u8,
HalfWord = crc::cr::REV_IN::HalfWord as u8,
/// Bits reversed by word. `0x1A2B3C4D` becomes `0xB23CD458`.
Word = crc::cr::REV_IN_A::Word as u8,
Word = crc::cr::REV_IN::Word as u8,
}

/// CRC unit configuration.
Expand Down Expand Up @@ -368,7 +381,7 @@ impl Config {
fn get_reverse_input(&self) -> u8 {
self.reverse_input
.map(|rev| rev as u8)
.unwrap_or(crc::cr::REV_IN_A::Normal as u8)
.unwrap_or(crc::cr::REV_IN::Normal as u8)
}

/// Set whether to reverse the bits of the output.
Expand Down
26 changes: 13 additions & 13 deletions src/dac.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -88,8 +88,8 @@ macro_rules! dac {
pub fn enable(self) -> $CX<$DAC, Enabled> {
let dac = unsafe { &(*$DAC::ptr()) };

dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
dac.cr.modify(|_, w| w.$en().set_bit());
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
dac.cr().modify(|_, w| w.$en().set_bit());

$CX {
_dac: PhantomData,
Expand All @@ -100,8 +100,8 @@ macro_rules! dac {
pub fn enable_unbuffered(self) -> $CX<$DAC, EnabledUnbuffered> {
let dac = unsafe { &(*$DAC::ptr()) };

dac.mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
dac.cr.modify(|_, w| w.$en().set_bit());
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(2) });
dac.cr().modify(|_, w| w.$en().set_bit());

$CX {
_dac: PhantomData,
Expand Down Expand Up @@ -130,19 +130,19 @@ macro_rules! dac {
T: DelayUs<u32>,
{
let dac = unsafe { &(*$DAC::ptr()) };
dac.cr.modify(|_, w| w.$en().clear_bit());
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
dac.cr.modify(|_, w| w.$cen().set_bit());
dac.cr().modify(|_, w| w.$en().clear_bit());
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
dac.cr().modify(|_, w| w.$cen().set_bit());
let mut trim = 0;
while true {
dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
dac.ccr().modify(|_, w| unsafe { w.$trim().bits(trim) });
delay.delay_us(64_u32);
if dac.sr.read().$cal_flag().bit() {
if dac.sr().read().$cal_flag().bit() {
break;
}
trim += 1;
}
dac.cr.modify(|_, w| w.$cen().clear_bit());
dac.cr().modify(|_, w| w.$cen().clear_bit());

$CX {
_dac: PhantomData,
Expand All @@ -153,7 +153,7 @@ macro_rules! dac {
/// Disable the DAC channel
pub fn disable(self) -> $CX<$DAC, Disabled> {
let dac = unsafe { &(*$DAC::ptr()) };
dac.cr.modify(|_, w| w.$en().clear_bit());
dac.cr().modify(|_, w| w.$en().clear_bit());

$CX {
_dac: PhantomData,
Expand All @@ -166,12 +166,12 @@ macro_rules! dac {
impl<ED> DacOut<u16> for $CX<$DAC, ED> {
fn set_value(&mut self, val: u16) {
let dac = unsafe { &(*$DAC::ptr()) };
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
}

fn get_value(&mut self) -> u16 {
let dac = unsafe { &(*$DAC::ptr()) };
dac.$dor.read().bits() as u16
dac.$dor().read().bits() as u16
}
}
};
Expand Down
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