fix cycle adding for store instructions

skyfloogle · Dec 26, 2024 · bd151c4 · bd151c4
1 parent 8601f60
commit bd151c4
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/source/3ds/drc_core.c b/source/3ds/drc_core.c
@@ -1276,6 +1276,7 @@ static int drc_translateBlock(void) {
                 ADD(10, 10, 1);
                 LDW_I(1, inst_cache[i + 1].PC);
                 ADD_I(10, 10, cycles & 0xFF, 0);
+                cycles = 0;
                 LDR_IO(2, 11, 68*4);
                 BLX(ARM_COND_NE, 2);
                 MSR(0);
@@ -1311,6 +1312,7 @@ static int drc_translateBlock(void) {
                 ADD(10, 10, 1);
                 LDW_I(1, inst_cache[i + 1].PC);
                 ADD_I(10, 10, cycles & 0xFF, 0);
+                cycles = 0;
                 LDR_IO(2, 11, 68*4);
                 BLX(ARM_COND_NE, 2);
                 MSR(0);
@@ -1346,6 +1348,7 @@ static int drc_translateBlock(void) {
                 ADD(10, 10, 1);
                 LDW_I(1, inst_cache[i + 1].PC);
                 ADD_I(10, 10, cycles & 0xFF, 0);
+                cycles = 0;
                 LDR_IO(2, 11, 68*4);
                 BLX(ARM_COND_NE, 2);
                 MSR(0);