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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++ 1,417 217 Updated Jan 2, 2025

source codes used during the Coursera course titled "Developing FPGA-accelerated cloud applications with SDAccel: Practice"

C++ 7 7 Updated Aug 27, 2020

📖 A simple and easy GraphQL tutorial to get started with GraphQL.

JavaScript 320 33 Updated Apr 19, 2024

Algorithmic C Datatypes

C++ 120 37 Updated Dec 18, 2024

Algorithmic C Digital Signal Processing (DSP) Library

C 47 15 Updated Dec 18, 2024

Algorithmic C Math Library

C++ 59 18 Updated Dec 18, 2024

A directory of Western Digital’s RISC-V SweRV Cores

SystemVerilog 859 132 Updated Mar 26, 2020

Random instruction generator for RISC-V processor verification

Python 1,043 332 Updated Aug 29, 2024

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

202 41 Updated Dec 3, 2020

An open standard Cache Coherent Fabric Interface repository

TeX 65 10 Updated Dec 6, 2019

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Verilog 312 49 Updated Jan 23, 2022

The GNU MCU Eclipse OpenOCD

C 235 62 Updated Sep 27, 2019

The GNU MCU Eclipse RISC-V Embedded GCC

C 77 17 Updated Sep 27, 2019

Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/

C 111 86 Updated Mar 24, 2021

Hardware implementation of ORAM

Verilog 22 1 Updated Jul 12, 2017

Mirror of official linux-stable tree, for quick forking handiness

C 3 1 Updated Sep 6, 2017

Buildroot source code using to create rootfs for NVDLA image

Makefile 10 2 Updated Dec 10, 2017

NVDLA modifications for GreenSocs GreenLib

PostScript 7 12 Updated Dec 12, 2017

NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)

C++ 18 17 Updated Aug 23, 2018

NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)

C 21 17 Updated Aug 23, 2018

Virtual Platform for NVDLA

C++ 140 86 Updated Aug 23, 2018

NVDLA SW

C++ 490 194 Updated Jan 28, 2021

RTL, Cmodel, and testbench for NVDLA

Verilog 1,774 572 Updated Mar 2, 2022

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Python 1,855 527 Updated Jan 3, 2025

Fully parametrizable combinatorial parallel LFSR/CRC module

Python 140 55 Updated Jan 30, 2023

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,643 1,019 Updated Mar 24, 2021

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

C 1,267 370 Updated Feb 14, 2022
Scala 109 24 Updated Oct 19, 2018

A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.

138 39 Updated Nov 16, 2017
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