Stars
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
source codes used during the Coursera course titled "Developing FPGA-accelerated cloud applications with SDAccel: Practice"
📖 A simple and easy GraphQL tutorial to get started with GraphQL.
A directory of Western Digital’s RISC-V SweRV Cores
Random instruction generator for RISC-V processor verification
Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
An open standard Cache Coherent Fabric Interface repository
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
ilg-archived / riscv-none-gcc
Forked from riscvarchive/riscv-gccThe GNU MCU Eclipse RISC-V Embedded GCC
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
nvdla / linux-stable
Forked from cerana/linux-stableMirror of official linux-stable tree, for quick forking handiness
Buildroot source code using to create rootfs for NVDLA image
nvdla / greenlib
Forked from socrocket/greenlibNVDLA modifications for GreenSocs GreenLib
NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)
NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Fully parametrizable combinatorial parallel LFSR/CRC module
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
OpenDLA / OpenDLA
Forked from silicontalks01/OpenDLAA discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.