Reduce cache_timeout to 0.5 seconds

sdss · Jan 15, 2024 · ed2aac7 · ed2aac7
1 parent d29902f
commit ed2aac7
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,7 +4,7 @@
 
 ### 🚀 New
 
-* Added a cache to the registers with default timeout 1 second.
+* Added a cache to the registers with default timeout 0.5 second.
 * `Modbus.read_group()` calls `Modbus.get_all()` instead of reading individual registers sequentially. Since during a `status` all groups are read in quick succession, and with caching, this results in much faster status outputs.
 
 ### ✨ Improved

diff --git a/python/lvmecp/etc/lvmecp.yml b/python/lvmecp/etc/lvmecp.yml
@@ -1,7 +1,7 @@
 modbus:
   host: 10.8.38.51
   port: 502
-  cache_timeout: 1
+  cache_timeout: 0.5
   registers:
     door_locked:
       address: 0