v1.0.0-alpha

Milestone release to track / celebrate the first successful baremetal boot of the CPU on the FPGA.

Known Issues:

• Scatter/gather instructions not implemented or planned.
• The FPGA image / SoC infrastructure is all Xilinx IP, not contained in the repository and is very slow due to the awful AXI interconnect.
• Formal proofs for all (carryless-)multiply, divide, modulo fail because they time out. The instruction functional units themselves are correct.