Fix la_test2 gl sim

scarv · Sep 19, 2021 · 2d40ac0 · 2d40ac0
1 parent 6e8caf1
commit 2d40ac0
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
@@ -97,13 +97,16 @@ void main()
 	// Set clk & reset to one
 	reg_la2_data = 0x00000003;
 
+        // DELAY
+        for (i=0; i<5; i=i+1) {}
+
 	// Toggle clk & de-assert reset
 	for (i=0; i<11; i=i+1) {
 		clk = !clk;
 		reg_la2_data = 0x00000000 | clk;
 	}
 
-	if (reg_la0_data == 0x05) {
+	if (reg_la0_data >= 0x05) {
 		reg_mprj_datal = 0xAB610000;
 	}