Skip to content
View saurav255's full-sized avatar

Block or report saurav255

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
saurav255/README.md

πŸ‘‹ Hey there! I'm Saurav Kumar (@saurav255)

animated-header

πŸ”­ Exploring the World of FPGA, Verilog HDL & Chip Design

πŸ‘€ What I’m into:

  • ✨ Hardware Modeling, FPGA Development & Verilog HDL
  • ✨ VLSI, Chip Design, IP Blocks
  • ✨ Programming in C, C++, Java, Python, Verilog HDL

🌱 Currently diving into:

  • βš™οΈ FPGA Development (Xilinx)
  • πŸ› οΈ Building open-source FPGA and hardware modeling projects
  • πŸ“ Exploring ASIC and VLSI chip design techniques

πŸ’žοΈ Let's Collaborate on:

  • πŸ“¦ FPGA, Verilog, VLSI Chip Design projects
  • πŸš€ IP Blocks and FPGA Projects
  • πŸ”§ Open-source hardware modeling projects

πŸ“« How to reach me:

Gmail GitHub LinkedIn X

⚑ Fun Fact:

If you look past your problems, the world is actually pretty beautiful 🌍


animated-footer

Popular repositories Loading

  1. Uart-Reciever-Fpga Uart-Reciever-Fpga Public

    Tcl 2

  2. saurav255 saurav255 Public

    Config files for my GitHub profile.

    1

  3. Fpga-Counter Fpga-Counter Public

    Tcl 1