Remove code setting IC_DATA_CMD.RESTART bit #827
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BTW, regarding the failing on-target tests, I already started to fix them. |
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The change seem correct to me; And yes, updating the expected stop/restart of the on-target-test will be a bit tedious. It was a pain to figure in the first place because of how latency can cause several events to be merged/undicernable. |
According to the datasheet, a restart is automatically triggered "if the transfer direction is changing from the previous command". The RESTART bit is only needed to trigger an unconditional RESTART sequence. According to the contract of I2c::transaction, "Data from adjacent operations of the same type are sent after each other without an SP or SR" and "Between adjacent operations of a different type an SR and SAD+R/W is sent". This looks like it is exactly what the hardware provides out of the box. (See: https://docs.rs/embedded-hal/1.0.0/ebedded_hal/i2c/trait.I2c.html#tymethod.transaction)
Some of the panic messages are longer than the default buffer, causing a lockup.
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According to the datasheet, a restart is automatically triggered "if the transfer direction is changing from the previous command". The RESTART bit is only needed to trigger an unconditional RESTART sequence.
According to the contract of I2c::transaction, "Data from adjacent operations of the same type are sent after each other without an SP or SR" and "Between adjacent operations of a different type an SR and SAD+R/W is sent". This looks like it is exactly what the hardware provides out of the box.
(See: https://docs.rs/embedded-hal/1.0.0/ebedded_hal/i2c/trait.I2c.html#tymethod.transaction)
This fixes #825. Unfortunately, it breaks some of the on-target tests, which expect the additional restart conditions.