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WIP: update
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@AkiyukiOkayasu
AkiyukiOkayasu committed Feb 14, 2024
1 parent 8603abd commit e917138
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Showing 10 changed files with 149 additions and 146 deletions.
20 changes: 10 additions & 10 deletions rp2040-hal/src/clocks/macros.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ macro_rules! clock {
fn await_select(&self, clock_token: &ChangingClockToken<Self>) -> nb::Result<(), Infallible> {
let shared_dev = unsafe { self.shared_dev.get() };

let selected = shared_dev.[<$reg _selected>].read().bits();
let selected = shared_dev.[<$reg _selected>]().read().bits();
if selected != 1 << clock_token.clock_nr {
return Err(nb::Error::WouldBlock);
}
Expand Down Expand Up @@ -136,7 +136,7 @@ macro_rules! clock {
pub fn reset_source_await(&mut self) -> nb::Result<(), Infallible> {
let shared_dev = unsafe { self.shared_dev.get() };

shared_dev.[<$reg _ctrl>].modify(|_, w| {
shared_dev.[<$reg _ctrl>]().modify(|_, w| {
w.src().variant(self.get_default_clock_source())
});

Expand All @@ -149,7 +149,7 @@ macro_rules! clock {
fn set_src<S: ValidSrc<$name>>(&mut self, src: &S)-> ChangingClockToken<$name> {
let shared_dev = unsafe { self.shared_dev.get() };

shared_dev.[<$reg _ctrl>].modify(|_,w| {
shared_dev.[<$reg _ctrl>]().modify(|_,w| {
w.src().variant(src.variant().unwrap_src())
});

Expand All @@ -160,7 +160,7 @@ macro_rules! clock {
}

fn set_self_aux_src(&mut self) -> ChangingClockToken<$name> {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| {
w.src().variant(self.get_aux_source())
});

Expand Down Expand Up @@ -269,13 +269,13 @@ macro_rules! divisable_clock {
$crate::paste::paste! {
impl ClockDivision for $name {
fn set_div(&mut self, div: u32) {
unsafe { self.shared_dev.get() }.[<$reg _div>].modify(|_, w| unsafe {
unsafe { self.shared_dev.get() }.[<$reg _div>]().modify(|_, w| unsafe {
w.bits(div);
w
});
}
fn get_div(&self) -> u32 {
unsafe { self.shared_dev.get() }.[<$reg _div>].read().bits()
unsafe { self.shared_dev.get() }.[<$reg _div>]().read().bits()
}
}
}
Expand All @@ -302,21 +302,21 @@ macro_rules! stoppable_clock {
impl StoppableClock for $name {
/// Enable the clock
fn enable(&mut self) {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| {
w.enable().set_bit()
});
}

/// Disable the clock cleanly
fn disable(&mut self) {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| {
w.enable().clear_bit()
});
}

/// Disable the clock asynchronously
fn kill(&mut self) {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>].modify(|_, w| {
unsafe { self.shared_dev.get() }.[<$reg _ctrl>]().modify(|_, w| {
w.kill().set_bit()
});
}
Expand Down Expand Up @@ -412,7 +412,7 @@ macro_rules! base_clock {
fn set_aux<S: ValidSrc<$name>>(&mut self, src: &S) {
let shared_dev = unsafe { self.shared_dev.get() };

shared_dev.[<$reg _ctrl>].modify(|_,w| {
shared_dev.[<$reg _ctrl>]().modify(|_,w| {
w.auxsrc().variant(src.variant().unwrap_aux())
});
}
Expand Down
8 changes: 4 additions & 4 deletions rp2040-hal/src/clocks/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -469,16 +469,16 @@ impl ClocksManager {
/// Read the clock gate configuration while the device is in its (deep) sleep state.
pub fn sleep_enable(&self) -> ClockGate {
ClockGate(
(u64::from(self.clocks.sleep_en1.read().bits()) << 32)
| u64::from(self.clocks.sleep_en0.read().bits()),
(u64::from(self.clocks.sleep_en1().read().bits()) << 32)
| u64::from(self.clocks.sleep_en0().read().bits()),
)
}

/// Read the clock gate configuration while the device is in its wake state.
pub fn wake_enable(&self) -> ClockGate {
ClockGate(
(u64::from(self.clocks.wake_en1.read().bits()) << 32)
| u64::from(self.clocks.wake_en0.read().bits()),
(u64::from(self.clocks.wake_en1().read().bits()) << 32)
| u64::from(self.clocks.wake_en0().read().bits()),
)
}

Expand Down
8 changes: 4 additions & 4 deletions rp2040-hal/src/gpio/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1045,11 +1045,11 @@ macro_rules! gpio {
// SAFETY: this function owns the whole bank that will be affected.
let sio = unsafe { &*$crate::pac::SIO::PTR };
if DynBankId::$bank == DynBankId::Bank0 {
sio.gpio_oe.reset();
sio.gpio_out.reset();
sio.gpio_oe().reset();
sio.gpio_out().reset();
} else {
sio.gpio_hi_oe.reset();
sio.gpio_hi_out.reset();
sio.gpio_hi_oe().reset();
sio.gpio_hi_out().reset();
}
}

Expand Down
52 changes: 26 additions & 26 deletions rp2040-hal/src/gpio/pin/pin_sealed.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ macro_rules! accessor_fns {
unsafe {
let sio = &*$crate::pac::SIO::PTR;
match pin.bank {
DynBankId::Bank0 => &sio.[<gpio_ $reg:lower>],
DynBankId::Qspi => core::mem::transmute(&sio.[<gpio_hi_ $reg:lower>]),
DynBankId::Bank0 => &sio.[<gpio_ $reg:lower>](),
DynBankId::Qspi => core::mem::transmute(&sio.[<gpio_hi_ $reg:lower>]()),
}
}
}
Expand All @@ -57,17 +57,17 @@ macro_rules! accessor_fns {
match pin.bank {
DynBankId::Bank0 => {
let gpio = unsafe { &*$crate::pac::IO_BANK0::PTR };
&gpio.gpio[usize::from(pin.num)].[<gpio_ $reg:lower>]
&gpio.gpio(usize::from(pin.num)).[<gpio_ $reg:lower>]()
}
DynBankId::Qspi => unsafe {
let qspi = &*$crate::pac::IO_QSPI::PTR;
match pin.num {
0 => core::mem::transmute(&qspi.gpio_qspisclk().[<gpio_ $reg:lower>]),
1 => core::mem::transmute(&qspi.gpio_qspiss().[<gpio_ $reg:lower>]),
2 => core::mem::transmute(&qspi.gpio_qspisd0().[<gpio_ $reg:lower>]),
3 => core::mem::transmute(&qspi.gpio_qspisd1().[<gpio_ $reg:lower>]),
4 => core::mem::transmute(&qspi.gpio_qspisd2().[<gpio_ $reg:lower>]),
5 => core::mem::transmute(&qspi.gpio_qspisd3().[<gpio_ $reg:lower>]),
0 => core::mem::transmute(&qspi.gpio_qspisclk().[<gpio_ $reg:lower>]()),
1 => core::mem::transmute(&qspi.gpio_qspiss().[<gpio_ $reg:lower>]()),
2 => core::mem::transmute(&qspi.gpio_qspisd0().[<gpio_ $reg:lower>]()),
3 => core::mem::transmute(&qspi.gpio_qspisd1().[<gpio_ $reg:lower>]()),
4 => core::mem::transmute(&qspi.gpio_qspisd2().[<gpio_ $reg:lower>]()),
5 => core::mem::transmute(&qspi.gpio_qspisd3().[<gpio_ $reg:lower>]()),
_ => unreachable!("Invalid QSPI bank pin number."),
}
},
Expand All @@ -85,15 +85,15 @@ macro_rules! accessor_fns {
DynBankId::Bank0 => {
let bank = &*$crate::pac::IO_BANK0::PTR;
match proc {
CoreId::Core0 => &bank.[<proc0_ $reg:lower>][usize::from(index)],
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>][usize::from(index)]),
CoreId::Core0 => &bank.[<proc0_ $reg:lower>](usize::from(index)),
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>](usize::from(index))),
}
}
DynBankId::Qspi => {
let bank = &*$crate::pac::IO_QSPI::PTR;
match proc {
CoreId::Core0 => core::mem::transmute(&bank.[<proc0_ $reg:lower>]),
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>]),
CoreId::Core0 => core::mem::transmute(&bank.[<proc0_ $reg:lower>]()),
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>]()),
}
}
};
Expand All @@ -111,11 +111,11 @@ macro_rules! accessor_fns {
let reg = match pin.bank {
DynBankId::Bank0 => {
let bank = &*$crate::pac::IO_BANK0::PTR;
&bank.[< dormant_wake_ $reg:lower>][usize::from(index)]
&bank.[< dormant_wake_ $reg:lower>](usize::from(index))
}
DynBankId::Qspi => {
let bank = &*$crate::pac::IO_QSPI::PTR;
core::mem::transmute(&bank.[< dormant_wake_ $reg:lower>])
core::mem::transmute(&bank.[< dormant_wake_ $reg:lower>]())
}
};
(reg, usize::from(offset))
Expand All @@ -136,17 +136,17 @@ where
match pin.bank {
DynBankId::Bank0 => {
let gpio = unsafe { &*pac::PADS_BANK0::PTR };
&gpio.gpio[usize::from(pin.num)]
&gpio.gpio(usize::from(pin.num))
}
DynBankId::Qspi => unsafe {
let qspi = &*pac::PADS_QSPI::PTR;
match pin.num {
0 => core::mem::transmute(&qspi.gpio_qspi_sclk),
1 => core::mem::transmute(&qspi.gpio_qspi_ss),
2 => core::mem::transmute(&qspi.gpio_qspi_sd0),
3 => core::mem::transmute(&qspi.gpio_qspi_sd1),
4 => core::mem::transmute(&qspi.gpio_qspi_sd2),
5 => core::mem::transmute(&qspi.gpio_qspi_sd3),
0 => core::mem::transmute(&qspi.gpio_qspi_sclk()),
1 => core::mem::transmute(&qspi.gpio_qspi_ss()),
2 => core::mem::transmute(&qspi.gpio_qspi_sd0()),
3 => core::mem::transmute(&qspi.gpio_qspi_sd1()),
4 => core::mem::transmute(&qspi.gpio_qspi_sd2()),
5 => core::mem::transmute(&qspi.gpio_qspi_sd3()),
_ => unreachable!("Invalid QSPI bank pin number."),
}
},
Expand All @@ -170,8 +170,8 @@ where
unsafe {
let syscfg = &*pac::SYSCFG::PTR;
match pin.bank {
DynBankId::Bank0 => &syscfg.proc_in_sync_bypass,
DynBankId::Qspi => core::mem::transmute(&syscfg.proc_in_sync_bypass_hi),
DynBankId::Bank0 => &syscfg.proc_in_sync_bypass(),
DynBankId::Qspi => core::mem::transmute(&syscfg.proc_in_sync_bypass_hi()),
}
}
}
Expand All @@ -183,11 +183,11 @@ where
let reg = match pin.bank {
DynBankId::Bank0 => {
let bank = &*pac::IO_BANK0::PTR;
&bank.intr[usize::from(index)]
&bank.intr(usize::from(index))
}
DynBankId::Qspi => {
let bank = &*pac::IO_QSPI::PTR;
core::mem::transmute(&bank.intr)
core::mem::transmute(&bank.intr())
}
};

Expand Down
10 changes: 6 additions & 4 deletions rp2040-hal/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -104,8 +104,10 @@ pub extern crate fugit;
pub fn reset() -> ! {
unsafe {
cortex_m::interrupt::disable();
(*pac::PSM::PTR).wdsel.write(|w| w.bits(0x0001ffff));
(*pac::WATCHDOG::PTR).ctrl.write(|w| w.trigger().set_bit());
(*pac::PSM::PTR).wdsel().write(|w| w.bits(0x0001ffff));
(*pac::WATCHDOG::PTR)
.ctrl()
.write(|w| w.trigger().set_bit());
#[allow(clippy::empty_loop)]
loop {}
}
Expand All @@ -122,8 +124,8 @@ pub fn halt() -> ! {
cortex_m::interrupt::disable();
// Stop other core
match crate::Sio::core() {
CoreId::Core0 => (*pac::PSM::PTR).frce_off.write(|w| w.proc1().set_bit()),
CoreId::Core1 => (*pac::PSM::PTR).frce_off.write(|w| w.proc0().set_bit()),
CoreId::Core0 => (*pac::PSM::PTR).frce_off().write(|w| w.proc1().set_bit()),
CoreId::Core1 => (*pac::PSM::PTR).frce_off().write(|w| w.proc0().set_bit()),
}
// Keep current core running, so debugging stays possible
loop {
Expand Down
10 changes: 5 additions & 5 deletions rp2040-hal/src/multicore.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ impl<'p> Core<'p> {
// since svd2rust doesn't really support multiple cores properly.
let peripherals = unsafe { pac::Peripherals::steal() };
let mut sio = Sio::new(peripherals.SIO);
sio.fifo().write_blocking(1);
sio.fifo.write_blocking(1);

entry();
loop {
Expand All @@ -195,11 +195,11 @@ impl<'p> Core<'p> {
// But there does not seem to be any obvious way to check that. A marker flag could be
// set from this method and cleared for the wrapper after `entry` returned. But doing
// so wouldn't be zero cost.
psm.frce_off.modify(|_, w| w.proc1().set_bit());
while !psm.frce_off.read().proc1().bit_is_set() {
psm.frce_off().modify(|_, w| w.proc1().set_bit());
while !psm.frce_off().read().proc1().bit_is_set() {
cortex_m::asm::nop();
}
psm.frce_off.modify(|_, w| w.proc1().clear_bit());
psm.frce_off().modify(|_, w| w.proc1().clear_bit());

// Set up the stack
// AAPCS requires in 6.2.1.2 that the stack is 8bytes aligned., we may need to trim the
Expand Down Expand Up @@ -235,7 +235,7 @@ impl<'p> Core<'p> {
// memory caches, and writes happen in-order.
compiler_fence(Ordering::Release);

let vector_table = ppb.vtor.read().bits();
let vector_table = ppb.vtor().read().bits();

// After reset, core 1 is waiting to receive commands over FIFO.
// This is the sequence to have it jump to some code.
Expand Down
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