update non-norm

svvptc.adoc

@@ -73,17 +73,17 @@ accesses by that hart to such PTEs.
 [NOTE]
 ====
 Typically, PTEs are marked as Valid by the operating system following a
-page-fault exception or during system calls for memory mapping. In cases like
-these, the trap handler usually employs an `SRET` instruction to return from the
-trap. The stores it executes to change the Valid bit of the PTEs from 0 to 1
-then become visible to implicit references to such PTEs within a bounded
-timeframe. This is applicable for instructions like the one causing the
-page-fault or those accessing new memory regions. A memory-management fence can
-be used to force immediate visibility of these PTE updates to all implicit
-references associated with instructions following the memory-management fence.
-But when Svvptc is implemented, visibility (in a bounded amount of time) is
-guaranteed and use of a memory-management fence is not required in these
-scenarios. While this approach might lead to an occasional gratuitous page-fault,
-the performance benefit of omitting the memory-management fence instructions
-outweighs the occasional cost of a gratuitous page-fault.
+page-fault exception or during system calls for memory mapping. In such cases,
+the trap handler commonly employs an `SRET` instruction to return from the trap.
+When Svvptc is implemented, the stores it executes to change the Valid bit
+of the PTEs from 0 to 1 then become visible to implicit references to those PTEs
+within a bounded timeframe. This visibility pertains to the instructions like
+the one causing the page-fault or those accessing new memory regions. A
+memory-management fence can be used to force immediate visibility of these PTE
+updates to all implicit references associated with instructions following the
+memory-management fence. However, when Svvptc is implemented, visibility (in a
+bounded amount of time) is guaranteed and use of a memory-management fence is
+not required in these scenarios. While this approach might lead to an occasional
+gratuitous page-fault, the performance benefit of omitting the memory-management
+fence instructions outweighs the occasional cost of a gratuitous page-fault.
 ====