Merge pull request #17 from ved-rivos/tsc_update1

add hart to qualify caches

svvptc.adoc

@@ -74,15 +74,15 @@ accesses by that hart to such PTEs.
 ====
 Svvptc relieves an operating system from executing certain memory-management
 instructions, such as `SFENCE.VMA` or `SINVAL.VMA`, which would normally be used
-to synchronize the address-translation caches when a memory-resident PTE is
-changed from Invalid to Valid. Synchronizing the address-translation caches with
-other forms of updates to a memory-resident PTE, including when a PTE is changed
-from Valid to Invalid, requires the use of suitable memory-management
-instructions. Svvptc guarantees that a change to a PTE from Invalid to Valid is
-made visible within a bounded time, thereby making the execution of these
-memory-management instructions redundant. The performance benefit of eliding
-these instructions outweighs the cost of an occasional gratuitous additional
-page fault that may occur.
+to synchronize the harts address-translation caches when a memory-resident PTE
+is changed from Invalid to Valid. Synchronizing the harts address-translation
+caches with other forms of updates to a memory-resident PTE, including when a
+PTE is changed from Valid to Invalid, requires the use of suitable
+memory-management instructions. Svvptc guarantees that a change to a PTE from
+Invalid to Valid is made visible within a bounded time, thereby making the
+execution of these memory-management instructions redundant. The performance
+benefit of eliding these instructions outweighs the cost of an occasional
+gratuitous additional page fault that may occur.
 
 Depending on the microarchitecture, some possible ways to facilitate
 implementation of Svvptc include: not having any address-translation caches, not