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Clarify permissions when the level extension is not implemented #501
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I mean, the RISC-V way is to get that information externally, for better or (generally) worse.
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That's true, happy to use hardwired to 1 instead if that sounds better to you?
I noticed I also need to update the infinite cap format to set those bits to zero/one.
This change is motivated by CHERI-Alliance/sail-cheri-riscv#3 since I noticed the M bit location was wrong.
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Reserved bits should be 0, and without levels the bits are reserved. When an extension adds meaning to those bits, the existing bit pattern should be unchanged in its meaning. I'm concerned the latter isn't true if the natural default is 1.
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I agree that reserved bits should be zero. The problem is that if we add new permissions, those will generally be '1' for permissive behaviour and '0' for restricted, so the natural default is 1 even though cores that don't implement this extension will be reporting zero and doing the permissive behaviour. I am not sure if this can really be fixed.
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You invert them, you have RES1 bits or you have separate feature enable bits. #502 is the short dump of thoughts I have on the matter, and that I've brought up many times over the years wanting people to think about this carefully with worked examples, to no avail.
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ok - so RES1 seems like the way to go
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For the in-memory format it seems like we would have to use inverted bit meaning? Otherwise if we use RES1 we end up having those permissions set to 0 for the null cap which sounds like it would be a problem?