Use Zvl/Zve to communicate VLEN/ELEN to target in debug tests (#567)

riscv-software-src · Jun 24, 2024 · e06a435 · e06a435
1 parent 1d3c10c
commit e06a435
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/debug/test b/debug/test
diff --git a/debug/testlib.py b/debug/testlib.py
@@ -134,6 +134,9 @@ def command(self, target, halted, timeout, with_jtag_gdb):
         else:
             isa = f"RV{self.harts[0].xlen}G"
 
+        if 'V' in isa[2:]:
+            isa += f"_Zvl{self.vlen}b_Zve{self.elen}d"
+
         cmd += ["--isa", isa]
         cmd += ["--dm-auth"]
 
@@ -159,8 +162,6 @@ def command(self, target, halted, timeout, with_jtag_gdb):
         if not self.support_haltgroups:
             cmd.append("--dm-no-halt-groups")
 
-        if 'V' in isa[2:]:
-            cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}")
 
         assert len(set(t.ram for t in self.harts)) == 1, \
                 "All spike harts must have the same RAM layout"