Merge pull request #309 from riscv-non-isa/patch-satp-bug

Patch satp bug
riscv-non-isa · Jan 30, 2023 · 89fbfec · 89fbfec
2 parents af1d7e1 + f3b0824
commit 89fbfec
Show file tree

Hide file tree

Showing 2 changed files with 6 additions and 3 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # CHANGELOG
-## [3.6.0] - 2022-10-11
+## [3.6.1] - 2023-01-28
+- Fix satp restore condition.
+
+## [3.6.0] - 2023-01-26
   - Removed the bugs in RVTEST_GOTO_LOWER_MODE macro
   - Removed the bugs in RVTEST_GOTO_MMODE macro and defined strap_routine directive.
   - Updated RVTEST_TRAP_SAVEAREA and RVTEST_TRAP_EPILOG macros to refine the definitions of per mode save area macros.
@@ -8,8 +11,6 @@
   - fixed the handling of when xTVEC was not initialized and also could not be written
   - rewritten the save_GPR macro to it now compiles
   - some miscellaneous optimizations
-
-=======
 
 ## [3.5.3] - 2022-11-22
   - Fix Canary definition according to sigalign.

diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
@@ -1398,9 +1398,11 @@ resto_\__MODE__\()edeleg:
 //FIXME: if N-extension or anything like it is implemented, uncomment the following
 //      csrw    CSR_XEDELEG, t2 //this handles S  mode restore
 .endif
+.if (\__MODE__\() != M)
 resto_\__MODE__\()satp:
         LREG    t2, xsatp_sv_addr(t1)           // restore saved xsatp
         csrw    CSR_XSATP,  t2
+.endif
 resto_\__MODE__\()scratch:
         LREG    t5, xscr_save_addr(t1)          // restore saved xscratch
         csrw    CSR_XSCRATCH, t5