Add 404 Page ASCII Art Design

404.html

@@ -9,3 +9,28 @@
 <h1>Page not found</h1>
 
 <p>The page you requested could not be found. Try using the navigation {% if site.search_enabled != false %}or search {% endif %}to find what you're looking for or go to this <a href="{{ '/' | absolute_url }}">site's home page</a>.</p>
+
+<pre style="overflow-x:scroll; font-size: 0.75rem; line-height:0.8rem;">
+____________/\\\________/\\\\\\\_______________/\\\____
+ __________/\\\\\______/\\\/////\\\___________/\\\\\____
+  ________/\\\/\\\_____/\\\____\//\\\________/\\\/\\\____
+   ______/\\\/\/\\\____\/\\\_____\/\\\______/\\\/\/\\\____
+    ____/\\\/__\/\\\____\/\\\_____\/\\\____/\\\/__\/\\\____
+     __/\\\\\\\\\\\\\\\\_\/\\\_____\/\\\__/\\\\\\\\\\\\\\\\_
+      _\///////////\\\//__\//\\\____/\\\__\///////////\\\//__
+       ___________\/\\\_____\///\\\\\\\/_____________\/\\\____
+        ___________\///________\///////_______________\///_____
+               _________________________________________________
+page_tdata ___/
+               _________________* oops, page AXI inactive
+page_tvalid __/                 \__________________________________
+            __________      ________________________________________
+page_tready           \____/
+</pre>
+
+<br>
+
+<p style="font-size: smaller;">
+  404 ASCII art generated from <a href="http://patorjk.com/software/taag/#p=display&f=Slant%20Relief&t=404" target="_blank">Text to ASCII Art Generator (TAAG)</a>.
+  Page AXI designed by <a href="https://wqzhao.org" target="_blank">Wuqiong Zhao</a>.
+</p>

README.md

@@ -1,2 +1,24 @@
-# rfsoc.dev
-rfsoc.dev Website
+# RFSoC.dev
+[rfsoc.dev](https://rfsoc.dev) Website
+
+## 404 Page Design
+```
+____________/\\\________/\\\\\\\_______________/\\\____
+ __________/\\\\\______/\\\/////\\\___________/\\\\\____
+  ________/\\\/\\\_____/\\\____\//\\\________/\\\/\\\____
+   ______/\\\/\/\\\____\/\\\_____\/\\\______/\\\/\/\\\____
+    ____/\\\/__\/\\\____\/\\\_____\/\\\____/\\\/__\/\\\____
+     __/\\\\\\\\\\\\\\\\_\/\\\_____\/\\\__/\\\\\\\\\\\\\\\\_
+      _\///////////\\\//__\//\\\____/\\\__\///////////\\\//__
+       ___________\/\\\_____\///\\\\\\\/_____________\/\\\____
+        ___________\///________\///////_______________\///_____
+               _________________________________________________
+page_tdata ___/
+               _________________* oops, page AXI inactive
+page_tvalid __/                 \__________________________________
+            __________      ________________________________________
+page_tready           \____/
+```
+
+404 ASCII art generated from [Text to ASCII Art Generator (TAAG)](http://patorjk.com/software/taag/#p=display&f=Slant%20Relief&t=404).
+Page AXI designed by [Wuqiong Zhao](https://wqzhao.org).

index.md

@@ -11,8 +11,3 @@ This website is presented by
 from the [University of California San Diego](https://ucsd.edu).
 
 Bookmark 🌟 the website link: [RFSoC.dev](https://rfsoc.dev).
-
-<div itemscope="" itemtype="https://schema.org/WebSite">
-  <meta itemprop="url" content="https://rfsoc.dev">
-  <meta itemprop="name" content="RFSoC.dev">
-</div>

my-practices/index.md

@@ -17,6 +17,15 @@ nav_order: 5
 - Note that overwriting a net of an interface will remove the connection to the corresponding interface net. Therefore, another manual connection is needed. This is especially important when we want to probe some signals of an interface using ILAs.
 - Write standard AXI/AXIS modules for the custom IP. This will make it easier to integrate your IP into the Vivado block design. Otherwise there can be some unexpected issues. Take special care of the `tready` signal. For instance, the buffering of a signal is not straightforward. It is easy just to use the `axi_register` or `axis_register` module from [AXI Utilities](https://github.com/alexforencich/verilog-axi) & [AXIS Utilities](https://github.com/alexforencich/verilog-axis) for Verilog.
 - All AXI/AXIS modules should have a register stage (preferably have a registered output). Therefore there will be no mismatched clocks which have to be manually handled every time we regenerate the IP.
+- Use TCL scripts can save a lot of time. One small example is to use the script to copy the generated `.bit`, `.hwh` and `.ltx` file:
+```tcl
+cd [get_property DIRECTORY [current_project]]
+file copy -force <proj>.runs/impl_1/<proj>_wrapper.bit <proj>.bit
+file copy -force <proj>.gen/sources_1/bd/<proj>/hw_handoff/<proj>.hwh <proj>.hwh
+file copy -force <proj>.runs/impl_1/<proj>_wrapper.ltx <proj>.ltx
+```
 
 ## Testing
+- I usually use LED lights as a bitstream version indicator, so I change the LED light pattern for each version of the bitstream. Therefore I can easily tell whether the new bitstream has been programmed successfully.
+
 ### Integrated Logic Analyzer (ILA)

publications/index.md

@@ -12,3 +12,6 @@ If you find this website useful, please consider citing our related work:
 [[ACM DL](https://dl.acm.org/doi/10.1145/3643832.3661865)] [[PDF](https://dl.acm.org/doi/pdf/10.1145/3643832.3661865)]
 2. W. Zhao *et al.*, [**Flexible High-Level Synthesis Library for Linear Transformations**](https://ieeexplore.ieee.org/document/10437992) in *IEEE TCAS-II ’24*.
 [[IEEE Xplore](https://ieeexplore.ieee.org/document/10437992)] [[PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)] [[GitHub](https://github.com/autohdw/flames)] [[website](https://flames.autohdw.com)]
+
+## Other Related Projects
+1. [Dual-Mode PSK Transceiver on SDR With FPGA](https://wqzhao.org/projects/sdr-psk-fpga) [[GitHub](https://github.com/Teddy-van-Jerry/sdr-psk-fpga)] [[report](https://go.wqzhao.org/sdr-psk-fpga)]

rf-analyzer/index.md

@@ -10,3 +10,15 @@ nav_order: 4
 ## Using AMD RF Analyzer
 
 ## Using PYNQ RF Analyzer
+Import [`xrfdc`](https://github.com/Xilinx/PYNQ/tree/93ddd21ab623883590a8c8b07f0b157b2855da4b/sdbuild/packages/xrfdc) to access RF data converter information:
+
+```python
+import xrfdc
+```
+
+Now the RF data converter IP has the `.IPStatus` attribute.
+For example:
+
+```python
+```
+