fix: format module code

renlabs-dev · Feb 29, 2024 · e8bc9b8 · e8bc9b8
1 parent 23f0b4d
commit e8bc9b8
Showing 1 changed file with 1 addition and 7 deletions.
diff --git a/pallets/subspace/src/module.rs b/pallets/subspace/src/module.rs
@@ -237,13 +237,7 @@ impl<T: Config> Pallet<T> {
 
         let weights: Vec<(u16, u16)> = Weights::<T>::get(netuid, uid)
             .iter()
-            .filter_map(|(i, w)| {
-                if *w > 0 {
-                    Some(((*i), (*w)))
-                } else {
-                    None
-                }
-            })
+            .filter_map(|(i, w)| if *w > 0 { Some((*i, *w)) } else { None })
             .collect();
         let stake_from: Vec<(T::AccountId, u64)> = StakeFrom::<T>::get(netuid, key);
         let registration_block = Self::get_registration_block_for_uid(netuid, uid);