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Merge pull request #168 from rcore-os/pl011
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Use pl011-uart crate for aarch64 example.
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qwandor authored Nov 27, 2024
2 parents 8e89be7 + 720b3a8 commit f8a3df1
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Showing 4 changed files with 6 additions and 68 deletions.
1 change: 1 addition & 0 deletions examples/aarch64/Cargo.toml
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Expand Up @@ -8,6 +8,7 @@ edition = "2021"
buddy_system_allocator = "0.10.0"
flat_device_tree = "3.1.1"
log = "0.4.22"
pl011-uart = "0.1.0"
smccc = "0.1.1"
spin = "0.9.8"
virtio-drivers = { path = "../.." }
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8 changes: 3 additions & 5 deletions examples/aarch64/src/main.rs
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Expand Up @@ -7,9 +7,7 @@ mod exceptions;
mod hal;
mod logger;
#[cfg(platform = "qemu")]
mod pl011;
#[cfg(platform = "qemu")]
use pl011 as uart;
use pl011_uart as uart;
#[cfg(platform = "crosvm")]
mod uart8250;
#[cfg(platform = "crosvm")]
Expand Down Expand Up @@ -50,11 +48,11 @@ use virtio_drivers::{

/// Base memory-mapped address of the primary PL011 UART device.
#[cfg(platform = "qemu")]
pub const UART_BASE_ADDRESS: usize = 0x900_0000;
pub const UART_BASE_ADDRESS: *mut u32 = 0x900_0000 as _;

/// The base address of the first 8250 UART.
#[cfg(platform = "crosvm")]
pub const UART_BASE_ADDRESS: usize = 0x3f8;
pub const UART_BASE_ADDRESS: *mut u32 = 0x3f8 as _;

#[global_allocator]
static HEAP_ALLOCATOR: LockedHeap<32> = LockedHeap::new();
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61 changes: 0 additions & 61 deletions examples/aarch64/src/pl011.rs

This file was deleted.

4 changes: 2 additions & 2 deletions examples/aarch64/src/uart8250.rs
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Expand Up @@ -18,9 +18,9 @@ impl Uart {
/// The given base address must point to the 8 MMIO control registers of an appropriate UART
/// device, which must be mapped into the address space of the process as device memory and not
/// have any other aliases.
pub unsafe fn new(base_address: usize) -> Self {
pub unsafe fn new(base_address: *mut u32) -> Self {
Self {
base_address: base_address as *mut u8,
base_address: base_address.cast(),
}
}

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