Top-Level Design

• CPU
  • finite state machine controller
  • datapath
• RAM (using the embedded memory block on the DE1-SoC)
• memory-mapped I/O interface (using the LEDs and switches on the DE1-SoC)

Instruction Set Architecture (ISA)

The ISA of this machine is designed to be Turing complete:

Terminology

Rn, Rd, Rm are 3 bit register number specifiers

im8 is an 8 bit immediate operand

im5 is a 5 bit immediate operand

<sh_op> are shift operations on Rm (LSL#1, LSR#1, ASR#1)

sh(R[m]) is the value of Rm after passing through the shifter and going into the Bin input of the ALU

sx(f) is a sign extension of the immediate value f to 16 bits

N, V, Z are the negative, overflow, and zero flags of the 3 bit status register

R[x] is the 16 bit value stored in register x

M[x] is the 16 bit value stored in RAM at address x

PC is the program counter

<label> is a syntax in the assembly language that indicates an instruction address

Syntax	Binary Encoding																Operation
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Register Transfer Instructions	opcode			op		3b			8b
MOV Rn, #<im8>	110			10		Rn			im8								R[n] = sx(im8)
									3b			2b		3b
MOV Rd, Rm, <sh_op>	110			00		000			Rd			sh		Rm			R[d] = sh(R[m])
Arithmetic/Logical Instructions	opcode			op		3b			3b			2b		3b
ADD Rd, Rn, Rm, <sh_op>	101			00		Rn			Rd			sh		Rm			R[d] = R[n] + sh(R[m])
AND Rd, Rn, Rm, <sh_op>	101			10		Rn			Rd			sh		Rm			R[d] = R[n] & sh(R[m])
CMP Rn, Rm, <sh_op>	101			01		Rn			000			sh		Rm			status = f(R[n] - sh(R[m]))
MVN Rd, Rm, <sh_op>	101			11		000			Rd			sh		Rm			R[d] = ~sh(R[m])
Memory Instructions	opcode			op		3b			3b			5b
LDR Rd, [Rn, #<im5>]	011			00		Rn			Rd			im5					R[d] = M[R[n] + sx(im5)]
STR Rd, [Rn, #<im5>]	100			00		Rn			Rd			im5					M[R[n] + sx(im5)] = R[d]
Branch Instructions	opcode			op		cond			8b
B <label>	001			00		000			im8								PC += sx(im8)
BEQ <label>	001			00		001			im8								if Z = 1 then PC += sx(im8)
BNE <label>	001			00		010			im8								if Z = 0 then PC += sx(im8)
BLT <label>	001			00		011			im8								if N != V then PC += sx(im8)
BLE <label>	001			00		100			im8								if (N != V or Z = 1) then PC += sx(im8)
Function Call/Return Instructions	opcode			op		Rn			8b
BL <label>	010			11		111			im8								R7 = PC, PC += sx(im8)
									3b			5b
BLX Rd	010			10		111			Rd			00000					R7 = PC, PC = R[d]
BX Rd	010			00		000			Rd			00000					PC = R[d]
Special Instructions
HALT	111			00		000			000			00000					wait