Merge pull request #1003 from Integral-Tech/refactor-qstring

refactor: use QString() as empty QString constructor
ra3xdh · Oct 21, 2024 · eacf586 · eacf586
2 parents fdd487d + 3445ad8
commit eacf586
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Showing 84 changed files with 139 additions and 139 deletions.
diff --git a/qucs-powercombining/qucspowercombiningtool.cpp b/qucs-powercombining/qucspowercombiningtool.cpp
@@ -787,7 +787,7 @@ QString QucsPowerCombiningTool::calcChebyLines(double RL, double Z0, double gamm
     {
         QMessageBox::warning(0, QObject::tr("Error"),
                              QObject::tr("Chebyshev weighting for N>7 is not available"));
-        return QString("");
+        return QString();
     }
     QString s;
     double sec_theta_m;// = cosh((1/(1.*N))*acosh((1/gamma)*fabs((RL-Z0)/(Z0+RL))) );
@@ -2065,7 +2065,7 @@ QString QucsPowerCombiningTool::ConvertLengthFromM(double len)
           return QString("%1 mm").arg(RoundVariablePrecision(conv));
   }
   }while(true);
-  return QString("");
+  return QString();
 }
 
 // Copied from Qucs misc class

diff --git a/qucs/components/component.cpp b/qucs/components/component.cpp
@@ -763,7 +763,7 @@ QString Component::spice_netlist(bool) {
 }
 
 QString Component::va_code() {
-    return QString(""); // ignore if not implemented
+    return QString(); // ignore if not implemented
 }
 
 // -------------------------------------------------------
@@ -772,7 +772,7 @@ QString Component::getNetlist() {
         case COMP_IS_ACTIVE:
             return netlist();
         case COMP_IS_OPEN:
-            return QString("");
+            return QString();
     }
 
     // Component is shortened.
@@ -795,7 +795,7 @@ QString Component::getSpiceNetlist(bool isXyce) {
             s.replace(" gnd ", " 0 ");
             return s;
         case COMP_IS_OPEN:
-            return QString("");
+            return QString();
     }
 
     // Component is shortened.
@@ -820,52 +820,52 @@ QString Component::getVerilogACode() {
             return s;
         case COMP_IS_OPEN:
         default:
-            return QString("");
+            return QString();
     }
 }
 
 QString Component::getExpression(bool) {
-    return QString("");
+    return QString();
 }
 
 QString Component::getEquations(QString, QStringList &) {
-    return QString("");
+    return QString();
 }
 
 QStringList Component::getExtraVariables() {
     return QStringList();
 }
 
 QString Component::getProbeVariable(bool) {
-    return QString("");
+    return QString();
 }
 
 QString Component::getSpiceModel() {
-    return QString("");
+    return QString();
 }
 
 QString Component::getNgspiceBeforeSim(QString sim, int lvl) {
     Q_UNUSED(sim) // To suppress warning
     Q_UNUSED(lvl)
-    return QString("");
+    return QString();
 }
 
 QString Component::getNgspiceAfterSim(QString sim, int lvl) {
     Q_UNUSED(sim) // To suppress warning
     Q_UNUSED(lvl)
-    return QString("");
+    return QString();
 }
 
 // -------------------------------------------------------
 QString Component::verilogCode(int) {
-    return QString("");   // no digital model
+    return QString();   // no digital model
 }
 
 // -------------------------------------------------------
 QString Component::get_Verilog_Code(int NumPorts) {
     switch (isActive) {
         case COMP_IS_OPEN:
-            return QString("");
+            return QString();
         case COMP_IS_ACTIVE:
             return verilogCode(NumPorts);
     }
@@ -882,14 +882,14 @@ QString Component::get_Verilog_Code(int NumPorts) {
 
 // -------------------------------------------------------
 QString Component::vhdlCode(int) {
-    return QString("");   // no digital model
+    return QString();   // no digital model
 }
 
 // -------------------------------------------------------
 QString Component::get_VHDL_Code(int NumPorts) {
     switch (isActive) {
         case COMP_IS_OPEN:
-            return QString("");
+            return QString();
         case COMP_IS_ACTIVE:
             return vhdlCode(NumPorts);
     }

diff --git a/qucs/components/component.h b/qucs/components/component.h
@@ -49,11 +49,11 @@ class Component : public Element {
   virtual QStringList getExtraVariables();
   virtual QString getProbeVariable(bool isXyce = false);
   virtual QString getSpiceModel();
-  virtual QString getSpiceLibrary() { return QString(""); }
+  virtual QString getSpiceLibrary() { return QString(); }
   virtual QString getNgspiceBeforeSim(QString sim, int lvl=0);
   virtual QString getNgspiceAfterSim(QString sim, int lvl=0);
-  virtual QString getVAvariables() {return QString("");};
-  virtual QString getVAExpressions() {return QString("");};
+  virtual QString getVAvariables() {return QString();};
+  virtual QString getVAExpressions() {return QString();};
   virtual void getExtraVANodes(QStringList& ) {};
   QString get_VHDL_Code(int);
   QString get_Verilog_Code(int);

diff --git a/qucs/components/d_flipflop.cpp b/qucs/components/d_flipflop.cpp
@@ -122,7 +122,7 @@ Element* D_FlipFlop::info(QString& Name, char* &BitmapFile, bool getNewOne)
 
 QString D_FlipFlop::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/dff_SR.cpp b/qucs/components/dff_SR.cpp
@@ -177,7 +177,7 @@ QString dff_SR::verilogCode( int )
 
 QString dff_SR::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/equation.cpp b/qucs/components/equation.cpp
@@ -124,7 +124,7 @@ QString Equation::getVAExpressions()
  */
 QString Equation::getExpression(bool isXyce)
 {
-    if (isActive != COMP_IS_ACTIVE) return QString("");
+    if (isActive != COMP_IS_ACTIVE) return QString();
 
     QStringList ng_vars,ngsims;
     getNgnutmegVars(ng_vars,ngsims);
@@ -172,7 +172,7 @@ QString Equation::getExpression(bool isXyce)
  */
 QString Equation::getEquations(QString sim, QStringList &dep_vars)
 {
-    if (isActive != COMP_IS_ACTIVE) return QString("");
+    if (isActive != COMP_IS_ACTIVE) return QString();
 
     QStringList ng_vars,ngsims;
     getNgnutmegVars(ng_vars,ngsims);
@@ -214,7 +214,7 @@ QString Equation::getNgspiceScript()
 
     QString s;
     s.clear();
-    if (isActive != COMP_IS_ACTIVE) return QString("");
+    if (isActive != COMP_IS_ACTIVE) return QString();
 
     for (int i=0;i<Props.count()-1;i++) {
         QStringList tokens;

diff --git a/qucs/components/ground.cpp b/qucs/components/ground.cpp
@@ -63,10 +63,10 @@ Element* Ground::info(QString& Name, char* &BitmapFile, bool getNewOne)
 // -------------------------------------------------------
 QString Ground::netlist()
 {
-  return QString("");
+  return QString();
 }
 
 QString Ground::spice_netlist(bool)
 {
-    return QString("");
+    return QString();
 }
diff --git a/qucs/components/jkff_SR.cpp b/qucs/components/jkff_SR.cpp
@@ -186,7 +186,7 @@ QString jkff_SR::verilogCode( int )
 
 QString jkff_SR::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/logical_buf.cpp b/qucs/components/logical_buf.cpp
@@ -137,7 +137,7 @@ Element* Logical_Buf::info(QString& Name, char* &BitmapFile, bool getNewOne)
 
 QString Logical_Buf::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/logical_inv.cpp b/qucs/components/logical_inv.cpp
@@ -154,7 +154,7 @@ Element* Logical_Inv::info(QString& Name, char* &BitmapFile, bool getNewOne)
 
 QString Logical_Inv::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/param_sweep.cpp b/qucs/components/param_sweep.cpp
@@ -81,7 +81,7 @@ void Param_Sweep::recreate(Schematic*)
 
 QString Param_Sweep::getNgspiceBeforeSim(QString sim, int lvl)
 {
-    if (isActive != COMP_IS_ACTIVE) return QString("");
+    if (isActive != COMP_IS_ACTIVE) return QString();
 
     QString s,unit;
     QStringList parameter_list = getProperty("Param")->Value.split( this->param_split_str );
@@ -166,7 +166,7 @@ QString Param_Sweep::getNgspiceBeforeSim(QString sim, int lvl)
 
 QString Param_Sweep::getNgspiceAfterSim(QString sim, int lvl)
 {
-    if (isActive != COMP_IS_ACTIVE) return QString("");
+    if (isActive != COMP_IS_ACTIVE) return QString();
 
     QString s;
     QStringList parameter_list = getProperty("Param")->Value.split( this->param_split_str );

diff --git a/qucs/components/spicefile.cpp b/qucs/components/spicefile.cpp
@@ -154,7 +154,7 @@ void SpiceFile::createSymbol()
 QString SpiceFile::netlist()
 {
   if(Props.at(1)->Value.isEmpty())
-    return QString("");  // no ports, no subcircuit instance
+    return QString();  // no ports, no subcircuit instance
 
   QString s = "Sub:"+Name;   // SPICE netlist is subcircuit
   for (Port *pp : Ports)

diff --git a/qucs/components/subcirport.cpp b/qucs/components/subcirport.cpp
@@ -104,20 +104,20 @@ Element* SubCirPort::info(QString& Name, char* &BitmapFile, bool getNewOne)
 // -------------------------------------------------------
 QString SubCirPort::netlist()
 {
-  return QString("");
+  return QString();
 }
 
 // -------------------------------------------------------
 QString SubCirPort::spice_netlist(bool)
 {
-    return QString("");
+    return QString();
 }
 
 // -------------------------------------------------------
 QString SubCirPort::vhdlCode(int)
 {
   if(Props.at(1)->Value != "out")
-    return QString("");
+    return QString();
 
   // Insert dummy buffer to avoid reading from an output port.
   QString s = "  net_out";
@@ -130,5 +130,5 @@ QString SubCirPort::vhdlCode(int)
 // -------------------------------------------------------
 QString SubCirPort::verilogCode(int)
 {
-  return QString("");
+  return QString();
 }
diff --git a/qucs/components/tff_SR.cpp b/qucs/components/tff_SR.cpp
@@ -177,7 +177,7 @@ QString tff_SR::verilogCode( int )
 
 QString tff_SR::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name;
     QString tmp_model = "model_" + Name;

diff --git a/qucs/components/vacomponent.cpp b/qucs/components/vacomponent.cpp
@@ -298,7 +298,7 @@ void vacomponent::createSymbol(QJsonObject json)
 
 QString vacomponent::spice_netlist(bool isXyce)
 {
-    if (isXyce) return QString("");
+    if (isXyce) return QString();
 
     QString s = SpiceModel + Name + " ";
     for(const auto pp: Ports) {

diff --git a/qucs/components/verilogfile.cpp b/qucs/components/verilogfile.cpp
@@ -97,7 +97,7 @@ QString Verilog_File::loadFile()
 
   QFile f(File);
   if(!f.open(QIODevice::ReadOnly))
-    return QString("");
+    return QString();
 
   QTextStream stream(&f);
   File = stream.readAll();   // QString is better for "find" function

diff --git a/qucs/components/vhdlfile.cpp b/qucs/components/vhdlfile.cpp
@@ -104,7 +104,7 @@ QString VHDL_File::loadFile()
 
   QFile f(File);
   if(!f.open(QIODevice::ReadOnly))
-    return QString("");
+    return QString();
 
   QTextStream stream(&f);
   File = stream.readAll();   // QString is better for "find" function
@@ -332,19 +332,19 @@ QString VHDL_File_Info::parsePorts(QString s, int j)
   Expr.setPattern("\\bport\\b");  // start of interface definition
   i = s.indexOf(Expr, j+1);
   if(i < 0)
-    return QString("");
+    return QString();
   // find opening (
   i = s.indexOf('(', i+4) + 1;
   if(i <= 0)
-    return QString("");
+    return QString();
 
   // find closing (
   p = i;
   j = i-1;
   do {
     j = s.indexOf(')', j+1);
     if(j < 0)
-      return QString("");
+      return QString();
     p = s.indexOf('(', p+1);
     if(p >= 0 && p > j) p = -1;
   } while (p >= 0);
@@ -395,19 +395,19 @@ QString VHDL_File_Info::parseGenerics(QString s, int j)
   Expr.setPattern("\\bgeneric\\b");
   i = s.indexOf(Expr, j+1);
   if(i < 0)
-    return QString("");
+    return QString();
   // find opening (
   i = s.indexOf('(', i+4) + 1;
   if(i <= 0)
-    return QString("");
+    return QString();
 
   // find closing (
   p = i;
   j = i-1;
   do {
     j = s.indexOf(')', j+1);
     if(j < 0)
-      return QString("");
+      return QString();
     p = s.indexOf('(', p+1);
     if(p >= 0 && p > j) p = -1;
   } while (p >= 0);

diff --git a/qucs/dialogs/matchdialog.cpp b/qucs/dialogs/matchdialog.cpp
@@ -817,7 +817,7 @@ QString MatchDialog::calcMatchingLC(double r_real, double r_imag, double Z0,
           0, tr("Error"),
           tr("Real part of impedance must be greater zero,\nbut is %1 !")
               .arg(Zreal));
-      return QString(""); // matching not possible
+      return QString(); // matching not possible
     }
 
     // In high-Q circuits, Zreal often becomes somewhat about -1e-16
@@ -1303,7 +1303,7 @@ QString MatchDialog::calcDoubleStub(double r_real, double r_imag, double Z0,
   {
     QMessageBox::warning(0, tr("Error"),
                 tr("It is not possible to match this load using the double stub method"));
-    return QString("");
+    return QString();
   }
 
   // Stubs susceptance
@@ -1432,7 +1432,7 @@ QString MatchDialog::calcChebyLines(double r_real, double r_imag, double Z0,
     QMessageBox::warning(
         0, QObject::tr("Error"),
         QObject::tr("Chebyshev weighting for N>7 is not available"));
-    return QString("");
+    return QString();
   }
 
   QString laddercode;

diff --git a/qucs/extsimkernels/ngspice.cpp b/qucs/extsimkernels/ngspice.cpp
@@ -400,7 +400,7 @@ QString Ngspice::getParentSWPscript(Component *pc_swp, QString sim, bool before,
             }
         }
     }
-    return QString("");
+    return QString();
 }
 
 /*!
-Original file line number
+Diff line change
@@ Expand Up @@
                 }
             }
         }
-        return QString("");
+        return QString();
     }
     /*!
@@ Expand Down @@