Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

add retry for stlink to prevent transfer error #1671

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

add retry for stlink to prevent transfer error #1671

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 13 additions & 2 deletions pyocd/probe/stlink/stlink.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,8 @@
from enum import Enum
from typing import (List, Optional, Sequence, Tuple, Union)
import usb.core
import time


from .constants import (Commands, Status, SWD_FREQ_MAP, JTAG_FREQ_MAP)
from ...core import exceptions
Expand Down Expand Up @@ -470,11 +472,20 @@ def _write_mem(self, addr: int, data: Sequence[int], memcmd: int, maxtx: int, ap

def read_mem32(self, addr: int, size: int, apsel: int, csw: int):
assert (addr & 0x3) == 0 and (size & 0x3) == 0, "address and size must be word aligned"
return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw)
for attempt in range(10):
try:
return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw)
except:
time.sleep(0.1)

def write_mem32(self, addr: int, data: Sequence[int], apsel: int, csw: int):
assert (addr & 0x3) == 0 and (len(data) & 3) == 0, "address and size must be word aligned"
self._write_mem(addr, data, Commands.JTAG_WRITEMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw)
for attempt in range(10):
try:
self._write_mem(addr, data, Commands.JTAG_WRITEMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel, csw)
return
except:
time.sleep(0.1)

def read_mem16(self, addr: int, size: int, apsel: int, csw: int):
assert (addr & 0x1) == 0 and (size & 0x1) == 0, "address and size must be half-word aligned"
Expand Down