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[HW] cva6: Increase AXI data width #91
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Make the Ariane AXI config independent of the peripheral AXI Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
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Thanks for the efforts, Nils! Great work, especially on CVA6's side! ;-)
Only not 100% clear why we are upsizing the I$ line width as well
@@ -11,7 +11,7 @@ index 78ab0bf..5a70ccd 100644 | |||
localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64 | |||
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width | |||
localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit | |||
localparam int unsigned ICACHE_LINE_WIDTH = 256; // in bit | |||
localparam int unsigned ICACHE_LINE_WIDTH = 512; // in bit |
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Do we need wider I$ lines as well?
@@ -11,7 +11,7 @@ index 78ab0bf..5a70ccd 100644 | |||
localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64 | |||
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width | |||
localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit | |||
localparam int unsigned ICACHE_LINE_WIDTH = 256; // in bit | |||
localparam int unsigned ICACHE_LINE_WIDTH = 512; // in bit | |||
// D$ | |||
- localparam int unsigned CONFIG_L1D_SIZE = 32*1024; | |||
- localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64 |
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Okay, this should be true by default, now
@mp-17 Can we merge this? I guess it is more of a question of, is this the configuration you used for ASAP? |
Let's rebase this, modify the changelog, and launch a backend run! |
Set Ariane's AXI data width to its data cache width (currently 512 bit)
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