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[HW/SW] Cheshire integration - Linux on FPGA #319
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Hi mp-17, |
Hwy @mrbilandi; Ara will soon be able to run applications on Linux. We plan to release PRs and instructions on how to do it using the Cheshire SoC. |
Hi @mp-17, |
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Co-authored-by: Vincenzo Maisto <[email protected]> Signed-off-by: Moritz Imfeld <[email protected]>
Co-authored-by: Vincenzo Maisto <[email protected]> Signed-off-by: Moritz Imfeld <[email protected]>
Co-authored-by: Vincenzo Maisto <[email protected]> Signed-off-by: Moritz Imfeld <[email protected]>
Co-authored-by: Vincenzo Maisto <[email protected]> Co-authored-by: Matteo Perotti <[email protected]> Signed-off-by: Moritz Imfeld <[email protected]> dfklj
Signed-off-by: Moritz Imfeld <[email protected]>
Signed-off-by: Moritz Imfeld <[email protected]>
Signed-off-by: Moritz Imfeld <[email protected]>
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Co-authored-by: Vincenzo Maisto <[email protected]>
Co-authored-by: Vincenzo Maisto <[email protected]>
The flow now also works with VCU11
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This is to prevent from CI broken links if the original install64 is not an artifact
Hi @mp-17 I'm experiencing issues with FPGA build flow. VIVADO bitgen fails over a timing violation. So far, I tried this with fresh clones on VIVADO 2019.1, 2020.2, 2023.2. Any clues what I might be missing here? For context,
Modifications I did: Line 17 in e0a2de9
Changed to: where vivado path is set in my env. variable. I had to remove this snippet
from
as a temporary fix to Illegal Cast operation issue Mentioned in : pulp-platform/cheshire#112 (comment) Other than that, its all default and clean. Any clues, pointers to the fixes are extremely appreciated. 😊 |
Hi @fulcrum34, Just as an easy check, do you have VIVADO 2022.1, by any chances? |
Hi @mp-17
here is the And this happens with Any project I have with ARA present. Even the ara_soc.sv from ara/main However, from the timing failure issue in the above comment, I noticed it originates from AXI. How do you manage the dependency conflicts in bender? Is there a guide or instructions about it? Thank you very much 😊 |
Hey @fulcrum34, I start with What flow are you using? By issuing This cannot create any conflicts by definition, and it should guarantee reproducibility. If you use Are you using |
Hi @mp-17
I spun up a quick GitHub Actions build to reproduce it here Clone Cheshire Repository - Line 374 Anyways, I ignored it and moved forward, got the linux image and bitsream (with vivado 2020.2). |
Add FPGA and bare-metal/OS Cheshire flow to Ara
Main PR: pulp-platform/cheshire#160
With this PR, we add FPGA support to Ara. The SoC and scripts used are from Cheshire, which instantiates Ara as a Bender submodule.
The relative paths in
${ARA_ROOT}/cheshire/sw
get a meaning only when Ara gets instantiated by Cheshire.Changelog
Fixed
Added
cva6-sdk
submodule.Changed
Checklist