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[HW] Add support for single lane configuration #194

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@sharafat-10xEngineers sharafat-10xEngineers commented Dec 14, 2022

PR for the single lane support

This PR focuses on single lane with VLEN = 128, 256, 512. Also Default rv64uv tests are not ready to check the functionality for single lane configuration.

Changelog

Changed

  • Changes from this PR handle single lane configuration in ara slide unit and lane sequencer.
  • Handle NrLanes == 1 case in the ara sequencer as there is no lane desynchronization problem in case of single lane.
  • Corrected vector length calculation for single lane by handling NrLanes == 1 case in lane sequencer where division of vector length is not required.
  • Corrected vector start calculation for single lane by handling NrLanes == 1 case in lane_sequencer where division of vstart is not required.
  • Handle a single lane case in the mask unit.
  • Fixes datapath for slide instructions and NrLanes == 1 case to support single lane configuration.
  • Update address generation logic of strided and indexed load store for AXIDataWidth = 32 when loading element of SEW=64.

Checklist

  • Automated tests pass
  • Changelog updated
  • Code style guideline is observed

@sharafat-10xEngineers sharafat-10xEngineers changed the title Single lane [HW] Add support for single lane configuration Dec 14, 2022
@fatimasaleem
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Hi @mp-17 can you enable the CI for this PR?

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mp-17 commented Dec 15, 2022

Thank you for opening this precious PR! I attach below the original draft work for reference (I closed the original PR):
#75

@sharafat-10xEngineers sharafat-10xEngineers force-pushed the single_lane branch 2 times, most recently from 3bb509b to cadc92b Compare December 20, 2022 08:07
@sharafat-10xEngineers
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Hi @mp-17, Kindly enable the latest CI for this PR.

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4 participants