SW-3191: svc: evt2: fix detect lines polarity

The modules are pulling the detect line low, but we actually need to check for high transitions because there is an inverter on the detect line. Testing Done: detected hotpluged modules on EVT2 Change-Id: Id14387d90c7350eae17cb386330255feb1a95828 Signed-off-by: Fabien Parent <[email protected]>
projectara · Apr 26, 2016 · 5bf1243 · 5bf1243
1 parent 591cd8a
commit 5bf1243
Showing 1 changed file with 11 additions and 6 deletions.
diff --git a/nuttx/configs/ara/svc/src/board-evt1.c b/nuttx/configs/ara/svc/src/board-evt1.c
@@ -611,37 +611,42 @@ DECLARE_MODULE_PORT_INTERFACE(evt2_module_4B, "module_4b",
                               evt2_module_4B_refclk_vreg_data, 8, WD_4B_DET,
                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_4B);
 #else
+/*
+ * Modules are pulling the detect lines low, but there is an inverter on the
+ * line between the connector and the SVC so the polarity is set to high
+ * for LATCH on the SVC.
+ */
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_1, "module_1",
                                evt1_5_module_1_vsys_vreg_data,
                                evt2_module_1_refclk_vreg_data, 13, WD_1_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_1_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_1);
+                               ARA_IFACE_WD_ACTIVE_HIGH, true, MOD_RELEASE_1);
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_2, "module_2",
                                evt1_5_module_2_vsys_vreg_data,
                                evt2_module_2_refclk_vreg_data, 11, WD_2_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_2_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_2);
+                               ARA_IFACE_WD_ACTIVE_HIGH, true, MOD_RELEASE_2);
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_3A, "module_3a",
                                evt1_5_module_3A_vsys_vreg_data,
                                evt2_module_3A_refclk_vreg_data, 4, WD_3A_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_3A_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true,
+                               ARA_IFACE_WD_ACTIVE_HIGH, true,
                                EVT2_MOD_RELEASE_3A);
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_3B, "module_3b",
                                evt1_5_module_3B_vsys_vreg_data,
                                evt2_module_3B_refclk_vreg_data, 2, WD_3B_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_3B_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_3B);
+                               ARA_IFACE_WD_ACTIVE_HIGH, true, MOD_RELEASE_3B);
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_4A, "module_4a",
                                evt1_5_module_4A_vsys_vreg_data,
                                evt2_module_4A_refclk_vreg_data, 6, WD_4A_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_4A_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_4A);
+                               ARA_IFACE_WD_ACTIVE_HIGH, true, MOD_RELEASE_4A);
 DECLARE_MODULE_PORT_INTERFACE2(evt2_module_4B, "module_4b",
                                evt1_5_module_4B_vsys_vreg_data,
                                evt2_module_4B_refclk_vreg_data, 8, WD_4B_DET,
                                ARA_IFACE_WD_ACTIVE_HIGH, LATCH_4B_DET,
-                               ARA_IFACE_WD_ACTIVE_LOW, true, MOD_RELEASE_4B);
+                               ARA_IFACE_WD_ACTIVE_HIGH, true, MOD_RELEASE_4B);
 #endif
 
 static struct interface *evt2_interfaces[] = {