ISA-MIPS-Coursework

2020-2021 Term 1 Instruction Set Architecture coursework: Verilog MIPS and test benches

Name		Name	Last commit message	Last commit date
Latest commit History 114 Commits
test		test
2_bit_registers.v		2_bit_registers.v
ALU.v		ALU.v
ALU_mult_tb.v		ALU_mult_tb.v
MIPS_tb.v		MIPS_tb.v
MUX_2.v		MUX_2.v
MUX_4.v		MUX_4.v
MUX_4_5bit.v		MUX_4_5bit.v
MUX_8.v		MUX_8.v
README.md		README.md
abswitch.v		abswitch.v
brancher.v		brancher.v
byte_decoder.v		byte_decoder.v
const_registers.v		const_registers.v
decoder.v		decoder.v
div.v		div.v
divu.v		divu.v
halter.v		halter.v
high_low_registers.v		high_low_registers.v
jump_shift.v		jump_shift.v
lrblock.v		lrblock.v
memory_block.v		memory_block.v
memoy_block2.v		memoy_block2.v
mips_cpu_bus.v		mips_cpu_bus.v
regfile.v		regfile.v
shift_l.v		shift_l.v
sign_extend.v		sign_extend.v
single_reg.v		single_reg.v
single_reg_1bit.v		single_reg_1bit.v
single_reg_1bit_en.v		single_reg_1bit_en.v
single_reg_2bit.v		single_reg_2bit.v
single_reg_en.v		single_reg_en.v
state_machine.v		state_machine.v
wordmask.v		wordmask.v

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